Southern University of Science and Technology

academic-body · research-org · Shenzhen, China · https://www.sustech.edu.cn/en/

Machines in the Atlas (2)

• SUSTech biased-erasure cavity qubit — DEMONSTRATED, 1 q, 29 Jan 2026
• SUSTech four-dual-rail-qubit processor — DEMONSTRATED (Nature Physics, 6 Mar 2026; arXiv 16 Apr 2025), 8 q, 6 Mar 2026 (Nature Physics; arXiv 16 Apr 2025)

Technologies its machines use

• Static nearest-neighbour lattice · 2
• Room-temperature electronics + per-qubit coax/flex · 2
• Mid-circuit erasure check · 2
• Erasure-adapted codes · 2
• Transmon · 1
• Bosonic cavity mode · 1
• Dual-rail (erasure) encoding · 1
• Tunable-coupler CZ / iSWAP · 1
• Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) · 1
• Multi-die packaging in one module (flip-chip, bump-bonded control die) · 1
• Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · 1
• 3D machined superconducting cavities · 1

Architectures

• Dual-rail erasure qubits

Mentioned in the briefs of

• Dual-rail (erasure) encoding
• Mid-circuit erasure check
• Multi-chip modules / l-couplers (same cryostat)
• Multi-die packaging in one module (flip-chip, bump-bonded control die)
• Bosonic cavity mode
• Erasure-adapted codes
• Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter)