Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) g_bos

Two bosonic cavity modes are never coupled directly. A nonlinear element between them — a driven DC-SQUID or SNAIL (superconducting nonlinear asymmetric inductive element) coupler, or a dispersively coupled transmon ancilla — is pumped at the mode-frequency difference, turning pump photons into a bilinear exchange (beamsplitter) or a conditional phase. Yale set the pattern in 2018 with an rf-driven 50:50 beamsplitter between two microwave memories D[471]; gate fidelities follow from 2023 D[472].

• b/e: entangling time ≈500 ns (10⁻⁶·³ s), deterministic; microwave drives from room-temperature electronics.
• d/g: modes linked through a shared coupler acting as a bus; 3D-machined cavity hardware, not planar chips.

The parametric beamsplitter rate reaches a few MHz, hence ~100 ns swaps D[472]; a conditional phase accumulates through a dispersive shift χ/2π ≈ 0.1–1 MHz, hence ~500 ns entangling gates D[84]. The floor is the ancilla, not the cavity: at ancilla T1 ≈ 50–100 µs against a 0.5-µs gate, ancilla error is ~10⁻² unless it is kept virtual or relabelled. Relabelling is the point: dual-rail does not lower total gate error but moves ~80% of it into heralded erasure (0.400(4)% control, 0.096(4)% target), leaving 0.029(6)% unheralded Pauli error and bit-flips at 2.8(4)×10⁻⁶ D[84]; located erasures buy ~5× more tolerable Pauli error at code level than depolarising noise P[402]. Failure modes: ancilla decay mid-gate (an erasure in dual-rail, a phase error elsewhere), ancilla dephasing, higher-Fock leakage no check sees, and for cats any gate term failing to commute with the two-photon dissipation. Moving the floor needs higher-coherence ancillas, virtual-ancilla or dissipative coupling, or a bias-preserving cat Hamiltonian — still theory P[81].

Best demonstrated: dual-rail cavity CZ, ~500 ns, erasure ≈0.5%/gate, post-selected Pauli 0.029(6)%, SPAM ≈0.02% D[84]fact. D-Wave markets it as "approximately 99.9%" C[473], neither the raw nor the post-selected value. Typical at scale lags: AWS's transmon check runs 384 ns, erasure 2.54(1)×10⁻²/check, residual 6.0(2)×10⁻⁴, bias 42(1) D[85]. No cat–cat CNOT exists on hardware P[81]. Dominant error term: unheralded Pauli error surviving post-selection, plus the check's false negatives.

Trapped ions realise the same qubit-conditioned bosonic primitive outside circuit QED: driving the red and blue motional sidebands together gives a spin-dependent conditional displacement of a motional mode, and free-boson rotations are applied as laser phase shifts; a three-ion ¹⁷¹Yb⁺ chain used them to simulate the dynamics of a Yukawa field model D[884].

Ancilla and coupler are aluminium-junction circuits in aluminium or tantalum films on silicon or sapphire; at Yale the modes are machined high-purity aluminium 3D cavities, etched to 10⁷–10⁸ Q, at D-Wave/Quantum Circuits 3D λ/4 coaxial cavities whose material and making are not published, while AWS's Ocelot holds its modes in thin-film coplanar-waveguide resonators on chip and Alice & Bob in thin-film tantalum circuits on sapphire D[80]fact. No merchant cavity supplier exists — Yale machines its own, D-Wave/Quantum Circuits name no supplier — so surface treatment is lab craft, not a qualified process. Below that, the generic superconducting chain: Bluefors, which absorbed pulse-tube maker Cryomech in 2023, and Oxford Instruments fact. Export exposure is the 2024 BIS rule: ECCN 4A906 (machines whose qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact), 3A904 (refrigerators ≥600 µW at 0.1 K), 3A901 (cryogenic amplifiers) G[301]. No per-cavity cost or yield is public.

Each cell needs a cavity drive, an ancilla drive and a dispersive ancilla readout, so lines run ahead of mode count. Erasure conversion adds latency: AWS resolves a check in 384 ns D[85], the cavity gate in ≈0.4–1 µs D[84]. That fits an FPGA-local loop but nothing off-chassis: NVQLink's 3.84 µs round trip suits syndrome processing, not heralding Cfact. The wall is geometric before electrical: a machined cavity is a cubic-centimetre object, so 10³ modes is a fridge-volume problem and 10⁶ needs planar or transmon variants.

The shared entangling primitive of two competing superconducting architectures, cat/GKP encoding and dual-rail erasure encoding. It requires a cavity mode plus an ancilla and replaces ancilla-free cat-CNOT schemes: hardware bought for erasure-convertibility or bias, a trade only dual-rail has cashed. It reaches the superconducting branch only. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset ≈ 1.44 µs on the cat-and-GKP architecture, whose largest term is two 500 ns gate layers, and ≈ 2.8 µs on the dual-rail one, with four. Empty neighbouring slots: a bias-preserving cat entangling gate, a merchant high-Q cavity process.

Headline figures come from randomised benchmarking on the composite two-mode system with post-selection on ancilla readout; the erasure fraction comes from that same readout, so false negatives fold into the "residual Pauli" bucket. A transmon-qutrit erasure design reports false positives ~2%, false negatives 6–8% P[405] — the order of what may be misattributed here. Theory keeps the surface-code threshold at least twice the Pauli value under imperfect checks, but only when the check is short against the cycle D[395]. Conflict: 0.029(6)% vs the 0.12% bound at depth D[84] vs "≈99.9%" C[473]; of the three, the measured decomposition is the best supported. SUSTech replicates the architecture, not the fidelity D[406]. Discard rates go unreported.

Not published: the amount of Alice & Bob's May-2026 Series B extension, and the post-selection discard rates of the dual-rail CZ and the beamsplitter swap.

Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| Quantum Circuits Inc. | developer | USA | Built the 500-ns dual-rail CZ; ships 8-qubit Seeker | D[84] |
| D-Wave Quantum | developer | USA | Owner since Jan 2026; funds and markets it | C[14] |
| Yale University | research | USA | Originated ancilla-mediated cavity gates | D[471] |
| AWS | developer | USA | Transmon erasure checks; Ocelot; CNOT theory | D[85] |
| Alice & Bob | developer | France | Cat gates; 18-cat Helium, no logical data | C[87] |
| Nord Quantique | developer | Canada | GKP bosonic gates; QBI Stage B | C[89] |

Money.
| Date | Actor | Event | Amount | Programme / lead | Status |
|---|---|---|---|---|---|
| 2025-01-28 | Alice & Bob | Series B (extension 2026-05-22, undisclosed) | €100M | AVP, Bpifrance | closed Cfact |
| 2025-11-04 | US DOE | centre renewal naming dual-rail | $125M | C2QA/NQISRC | awarded G[474] |
| 2025-11-06 | DARPA | Stage B, 11 teams, Alice & Bob cut | ≤$15M | QBI | official G[65] |
| 2026-01-20 | D-Wave | M&A: Quantum Circuits | $550M | — | closed C[14] |
| 2026-05-18 | Nord Quantique | equity at $1.4B valuation | $30M | — | closed C[89] |
| 2026-08-06 | D-Wave | H1-2026 revenue | $5.9M (−67% YoY) | — | reported C[15] |

Market & supply chain. Nobody sells into this mechanism: it rides the refrigerator and junction chains common to all superconducting qubits, plus one unshared step, 3D cavity machining, which is the single point of failure. Helium's ~40 kW is the family's only public power figure C[87]. It pays for G2 and is a credible G3 candidate via dual-rail, not G4: the cat resource case rests on a phase-flip rate two orders below measurement, and D-Wave's Λ = 27 is a simulation of its own error model Sfact.

IP & standards. Amazon Technologies holds US 11,748,652 B1 (heralding of amplitude-damping decay, granted 2023-09-05), reading directly on heralded-decay dual-rail embodiments G[336] — awkward for rivals, since AWS alone needs no licence. No Yale or Quantum Circuits family surfaced in a dual-rail patent search fact. No litigation, no standards body.

Roadmaps & track record. D-Wave/Quantum Circuits (2026-06, for 2032: 100 logical at Λ = 10, via 17 qubits in 2026) — gate published, no system delivered as of 4 Sep 2026 Pfact; best physics, unproven as product. Alice & Bob (2023, for 2030: 2,000 cats, 100 logical, 10⁻⁶) — Helium shipped without logical data, no Stage B slot; unverified. Nord Quantique (2024, for 2029: 100+ logical at 1:1) — capitalised, unproven. AWS — Ocelot delivered, cat–cat CNOT still theory; claims have not outrun measurements.

Strategic reading. If erasure conversion scales the winners own large superconducting fabs, not bosonic specialities: the mechanism is portable, and IBM, Google or Rigetti could bolt an ancilla check onto existing transmons without 3D cavities P[405]. That is the substitution threat to D-Wave's $550M purchase, which concentrates Yale-lineage IP but buys no fab moat. Losers if it fails: the cat roadmaps, whose economics rest on a 100× resource reduction the measured phase-flip rate does not support.

Confirm/demote in 12–24 months: a cat–cat CX on hardware; a dual-rail gate below 0.01% post-selected Pauli outside Quantum Circuits; a delivered 17-qubit system with its promised 2× logical-versus-physical error reduction; a published discard rate. Best case 2029: erasure conversion becomes a standard transmon add-on. Worst case: cat–cat gates stay theory and 3D cavities stall on volume. Open: does the erasure fraction hold at depth 10³; the true false-negative rate; can it be planarised without losing Q; does D-Wave fund Quantum Circuits through 2028 on $5.9M half-year revenue. Watch QBI Stage C.