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AWS Ocelot

AWS Center for Quantum Computing

AWS Ocelot

AWS Center for Quantum Computing · superconducting circuits · DEMONSTRATED (Feb 2025) · 9 physical qubits · access: lab-only (no cloud access)

Register profile — the machine's variant of its architecture

qubit type: dissipatively stabilised cat qubits (two-photon dissipation via buffer modes), best operating point alpha^2 ~ 1.5
gate mechanism: noise-biased cat-transmon CX with chi-matching; CX cycle 3 us, QEC cycle 2.8 us
connectivity: 1-D repetition-code chain, d=3 and d=5
control: room-temperature control
control placement: room-temp
readout: multiplexed dispersive readout of the transmon ancillas
gate evidence: a benchmark paper with its protocol
decoder mode: offline — syndromes decoded after the run
codes: cat_repetition, two-legged-cat
flags: no distance scaling shown

Technologies by layer — the machine's cell per layer

1 Qubit carrier
Bosonic cavity mode · primary ▣ Fig. 1a-c (storage modes S1-S5, buffers B1-B5); §II ✅
5 cat data modes in CPW resonators (5.24–5.41 GHz), stabilised by two-photon dissipation via 5 buffer modes; storage T1 >60 µs, T2 >80 µs
2 Encoding
Cat-code encoding (biased noise) · primary ▣ Fig. 1e (cat Wigner functions), Fig. 1f (bit-/phase-flip times) ✅
two-legged cat, |α|² swept 1→4, best ≈1.5; at |α|²=2 bit-flip >1 ms, phase-flip 27–33 µs, noise bias >30 (Feb 2025)
3 Gate mechanism
Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) · primary ▣ Fig. 2 (noise-biased CX gate); §III ✅
noise-biased cat–transmon CX, ancilla in |g⟩+|f⟩ with χ-matching; CX cycle 3 µs; per-cycle bit-flip 3.5(4)e-3, phase-flip 9.6(4)e-2
4 Connectivity / transport
Static nearest-neighbour lattice · primary ▣ Fig. 1a-b,d (5 cats + 4 ancillas, tunable couplers C_ij); §II ✅
1-D repetition-code chain of 5 cats + 4 transmon ancillas: d=3 (two 3-qubit subsections) and d=5 (full array); no 2-D code
5 Control
Room-temperature electronics + per-qubit coax/flex · primary ▤ App. B (Control lines and fridge setup) 🔎
room-temperature control; ~19 microwave modes (buffers, readout, Purcell and bandpass filters, tunable couplers) on a 9-qubit device
6 Readout
Dispersive microwave readout (+TWPA, Purcell) · primary ▤ ✅
multiplexed dispersive readout of the 4 fixed-frequency transmon ancillas through Purcell-filtered readout resonators
7 Code
Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) · primary ▣ Fig. 3 (phase-flip correction circuit), Fig. 5 (logical memory performance); §IV-VI ✅
two-legged cat ⊗ repetition code; logical error/cycle d=3 1.75(2)%, d=5 1.65(3)% at |α|²≈1.5 ⇒ Λ≈1.06 (Feb 2025)
8 Decoder
MWPM / Sparse Blossom (+ correlated matching) · primary ▤ App. H (Repetition Code Data Analysis) 🔎
1-D matching decoder run offline; no real-time decoder claimed, no decode latency published vs 2.8 µs QEC cycle
— none — nothing in this layer ▤ App. H (Repetition Code Data Analysis) 🔎
no real-time decoder: 1-D matching run offline only
9 Interconnect
Multi-die packaging in one module (flip-chip, bump-bonded control die) · primary ▤ App. A (Device fabrication) ✅
two dies flip-chip bonded with indium bumps in one module: Al die 16×14 mm² (junctions, buffers, transmons) + Ta die 20×20 mm² (storage modes)
10 Manufacturing
Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▤ App. A (Device fabrication) ✅
separately fabricated Al die (nonlinear elements) and Ta die (high-Q storage) on high-resistivity Si, decoupling Ta growth from junction processing

Standard records

2Q error under full-width parallel operation → 0.096 · typical (CX phase-flip per cycle; bit-flip 3.5e-3, bias >25)
Feb 2025 · source
idle / memory error per round → 0.0175 · typical (d=3; d=5 gives 1.65e-2, so Lambda ~1.06)
the only published two-distance bosonic-concatenated result · Feb 2025 · source
T1 relaxation → 1.0 ms · best-of-line (cat bit-flip time at photon number 2)
Feb 2025 · source
T2 coherence (echo/DD) → 27 µs · typical (phase-flip time, 27-33 us)
Feb 2025 · source
evidence: ✅ 8 / 11

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 1 — Figure 1: Repetition code of bosonic qubits. (a) Schematic diagram of the repetition code device. Data qubits S1,⋯,S5,, (blue) are encod external image — opens at the source
Drawings and plots. (a) Repetition-code schematic: five cat data qubits (cyan), each stabilised by a buffer mode (green), checked by four transmon ancillas (orange) that flag a phase-flip (Z) error; (b) chip layout drawing (1 mm scale bar) with storage resonators S1–S5; (c, d) close-ups of a buffer with its multi-pole filter and an ancilla with couplers and readout; (e) Bloch sphere of cat states; (f) bit-flip time rising exponentially and phase-flip time falling with mean photon number. From arXiv 2409.13025, Putterman et al., 'Hardware-efficient quantum error correction via concatenated bosonic qubits'. Superconducting cat qubits suppress bit flips in hardware, so the outer code only has to catch phase flips.
Fig. 6 — Figure 6: Wiring diagram. Room temperature and fridge setup for one unit cell. Eccosorb filters, room temperature switches for toggling between characterization external image — opens at the source
A wiring drawing traces every control and readout line of one unit cell from room-temperature instruments (network analyser, waveform generators) down through the 50 K, 4 K, 100 mK and 10 mK stages of a refrigerator. It comes from arXiv 2409.13025 by Putterman et al. on concatenated bosonic qubits. It illustrates room-temperature electronics with per-qubit coaxial lines for a cat-qubit device: attenuators, filters, isolators, HEMT and travelling-wave parametric amplifiers. Notice separate buffer, storage, coupler and ancilla lines.