Cat-code encoding (biased noise) enc_cat

A qubit spanned by two coherent states of a cavity mode, held there by engineered two-photon exchange with a lossy buffer. Bit-flips must cross phase space between the lobes, exponentially suppressed in n̄; one photon loss flips the phase, linear in n̄. Demonstrated from about 2020 (Lescanne, Leghtas and colleagues), commercialised by Alice & Bob and AWS. It has no gate time or readout of its own; its only product is the asymmetry.

Γ_Z ≈ n̄/T1: the encoding turns cavity lifetime directly into logical quality, and photon number buys bit-flip suppression at a linear price. Ocelot closes the loop: at n̄ = 2 the storage lifetime is 57–68 µs D[80]. Run that arithmetic at the operating point the estimates assume, n̄ ≈ 19 and 10⁻³ phase-flip per cycle, and the required cavity T1 is n̄·t/p ≈ 53 ms S[80], [95]. The best published cavity memory is 25.6 ms, built by decoupling the mode from its ancilla — the opposite of what a stabilised cat does D[319]. That is the floor: the qubit-count argument is a claim about cavity lifetime under strong drive. What moves it: lower single-photon loss at high pump power, or squeezed cats D[78].

Phase-flip dominates: ~10⁻¹ per cycle where a code has run, against the ~10⁻³ assumed; bit-flip suppression stopped being the problem two years ago.

The 9.6×10⁻² is the phase-flip error of the CX gate at n̄ = 2, not a per-QEC-cycle figure; the noise bias is > 25 under the CX and > 30 idle, and the "27–33" in circulation are phase-flip times in µs, not bias values D[80]. The 44-minute mean bit-flip time of the 12-cat chip (September 2025) is preliminary and vendor-published, with no peer-reviewed follow-up, and the vendor's roadmap page gives a 252-minute peak for the same period. The 53 ms cavity-lifetime requirement is derived from Γ_Z ≈ n̄/T1 under the estimates' own assumptions; neither source states it. Nord Quantique's QBI Stage B award [65] funds its GKP route, which does not use this encoding.

It has no fabrication step of its own, adding a continuous parametric pump and buffer mode to the host cavity. That pump is the I/O cost: a drive line, a pump line and a readout chain per cat — through a shared ancilla transmon on Ocelot, through the buffer at Alice & Bob Cfact. Ocelot spends five buffers and four ancilla transmons on five cats D[80]. At 10³ cats the wall is pump-line count and pump heating in one dilution unit; 10⁴–10⁶ needs multiplexed cryogenic drive, undemonstrated here. Supply chain and export exposure are the host cavity's.

Architecture: bosonic cavity qubits — cat and GKP, where it is the primary encoding. Requires a bosonic cavity mode; provides the biased inner qubit for repetition-cat and LDPC-cat concatenation and for a cat–cat CNOT. It replaces the bare two-level encoding, competes with GKP and conflicts with the unbiased surface code. Derived round 1.44 µs, gate-set, against the measured 2.8 µs syndrome cycle D[80]. Verification: the distance-3 and distance-5 points were taken at n̄ = 1 and n̄ = 1.5, so "flat with distance" mixes distance with operating point D[80]. The 44-minute mean bit-flip is preliminary; the same vendor's roadmap quotes a 252-minute peak from that run C[77]C[412].

Money.
2025-01-28 · Alice & Bob · Series B · €100 M · — · closed fact
2026-05-22 · Alice & Bob · Series B extension · undisclosed · NVentures lead · closed C[88]

Market & supply chain. Nothing is sold at this layer; the encoding is a design choice on the cavity supply chain, bought as a promise about G3 and G4. Alice & Bob's business rests on it.

IP & standards. No dated patent family specific to cat-code encoding was found; filings attach to gates, pumps and readout.

Roadmaps & track record. The published ladder runs Helium (18 cats, 1 logical, 10⁻², delivered 2026-06) → Lithium (48/4, 10⁻³) → Beryllium (250/5, 10⁻⁴) → Graphene (2,000/100, 10⁻⁶, 2030) R[412]. Chips arrive on time, but no logical error rate has been published for any, so every defining number is a promise. AWS has published no cat roadmap past Ocelot.

Strategic reading. If phase-flip per cycle falls two orders, cat encoding wins the physical-qubit count; if not, the branch is a memory technology and the budget goes to qLDPC or dual-rail erasure.

Confirm by 2027 if phase-flip per cycle falls below 10⁻² with bias above 100 at fixed n̄; demote the efficiency claims if it stays near 10⁻¹. Best case 2029: a cat at n̄ ≥ 5 with millisecond lifetime under active stabilisation. Worst case: bias saturates and the 758-cat and 126,133-cat estimates stay unreachable S[95], [96]. Open: does squeezing survive multi-qubit operation; can pump power rise without loading T1? Watch Lithium and any Ocelot successor.