Alice & Bob Helium 2 ("Galvanic Cat")

Raveh Neeman

doi:10.5281/zenodo.22674814

Alice & Bob

Alice & Bob Helium 2 ("Galvanic Cat")

Alice & Bob · superconducting circuits · DEMONSTRATED (preliminary) (25 Sep 2025) · 12 physical qubits · access: lab

architecture: Bosonic cavity qubits — cat and GKP · Open on the map

Register profile — the machine's variant of its architecture

qubit type: dissipatively stabilised, galvanically coupled, transmon-free cat qubits at n-bar = 11

gate mechanism: Z gate 94.2% in 26.5 ns; no cat-cat CNOT anywhere

connectivity: 1-D repetition chain

control: room-temperature control

control placement: room-temp

readout: dispersive

gate evidence: no published figure

codes: two-legged-cat

flags: not peer-reviewed, phase-flip time unpublished

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Bosonic cavity mode · primary ▨ ✅ 12-cat-qubit chip, galvanically coupled, transmon-free cats at n̄=11; bit-flip >1 h (33–60 min 95% CI), Sep 2025, preliminary
2 Encoding	Cat-code encoding (biased noise) · primary ▨ ✅ two-legged cat at n̄=11: bit-flip >1 h (33–60 min 95% CI); phase-flip time not measured in that run (Sep 2025)
3 Gate mechanism	Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) · primary ▨ ✅ Z gate 94.2% fidelity in 26.5 ns (Sep 2025); no cat–cat CNOT demonstrated
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▨ 🔎 1-D repetition chain on the 12-cat chip
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▨ 🔎 room-temperature control
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ◌ 🔎 dispersive readout
7 Code	Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) · primary ▨ 🔎 two-legged cat at n̄=11; register also lists squeezed cat (×160 bit-flip lifetime, no phase-flip penalty, Mar 2025); no logical error rate
8 Decoder	— none — nothing in this layer ▨ 🔎 no decoder published for any Alice & Bob device
9 Interconnect	— none — nothing in this layer ◌ 🔎 monolithic single 12-cat chip, no interconnect
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ◌ 🔎 galvanically coupled transmon-free cat circuits on one planar chip; fab process not published (Boson 3's memory was a quarter-wave coplanar resonator in tantalum on sapphire: Réglade et al., Nature 629, 778, 2024)

Standard records

1Q gate time → 27 ns · typical (Z gate at 94.2% fidelity)

Sep 2025 · source

bit-flip time (cat qubit, protected axis) → 3600 s · cat bit-flip time at photon number 11 (the protected axis of a cat qubit, not a T1; the top of the quoted interval)

33-60 min, 95% CI, company release; phase-flip time at the same point is not published · Sep 2025 · source

evidence: ✅ 3 / 10