Alice & Bob Graphene

Raveh Neeman

doi:10.5281/zenodo.22674814

Alice & Bob

Alice & Bob Graphene

Alice & Bob · superconducting circuits · PLANNED (2030) · 2000 physical qubits · access: n/a

architecture: Bosonic cavity qubits — cat and GKP · Open on the map

Register profile — the machine's variant of its architecture

qubit type: dissipatively stabilised cat qubits

gate mechanism: bias-preserving cat-cat CNOT required but only a Jul 2026 theory proposal exists

connectivity: low-weight 2-D stabilisers, short-range interactions

control: room-temperature control

control placement: room-temp

readout: dispersive

gate evidence: a published figure (source class not yet tagged)

codes: ldpc_cat

flags: rests on an assumption

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Bosonic cavity mode · primary ▥ ✅ dissipatively stabilised cat qubits; roadmap target Graphene: 100 high-fidelity logical qubits by 2030
2 Encoding	Cat-code encoding (biased noise) · primary ▣ Abstract (ε≈0.1%); Table I; Fig. 5c (cat-qubit circuit-level model) ✅ cat encoding; LDPC-cat design assumes physical phase-flip ≈0.1%
3 Gate mechanism	Bias-preserving cat–cat CNOT · primary ▤ Table I (ε_CNOT=1.6e-2); §V (current state of the art) ✅ bias-preserving cat–cat CNOT required; not demonstrated by anyone, only a Jul 2026 theory proposal exists Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) · alternate ▥ 🔎 bosonic single-cat gates (Z gate 26.5 ns shown on Helium 2); bias-preserving cat–cat CNOT not demonstrated
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▣ Fig. 2 (H×L lattice), Fig. 4 ([136,34,22] layout), Fig. 9; §V Chip layout ✅ short-range interactions, low-weight 2-D stabilisers (LDPC-cat design)
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▥ 🔎 room-temperature control
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ◌ 🔎 dispersive readout
7 Code	Bosonic concatenation (repetition-cat, LDPC-cat, GKP+qLDPC) · primary ▣ Fig. 3, Fig. 9 ([165,34,22] layout); §III (758 cats) ✅ LDPC-cat [[165+8ℓ, 34+2ℓ, 22]]: 100 logical qubits at ε_L ≤1e-8/cycle on 758 cats; elevator codes (Jan 2026) claim ~1e4× lower logical error
8 Decoder	— none — nothing in this layer ▤ App. C (BP+OSD) ✅ no decoder published for any Alice & Bob device
9 Interconnect	— none — nothing in this layer ▣ Fig. 9 (memory + compute layers); §V Chip layout ✅ monolithic single module, no interconnect
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▣ Fig. 9 (flip-chip two-layer layout) ✅ superconducting cat-qubit chip (planned 758 cats); fab process not published

evidence: ✅ 8 / 11