Bias-preserving cat–cat CNOT g_catcnot

An entangling gate acting directly between two dissipative cat qubits, no transmon ancilla in the middle, preserving the bit-flip/phase-flip asymmetry through the interaction. Every cat CX in hardware is cat–transmon; the cat–cat version is what cat-code resource estimates silently assume. The first coherent (unitary) scheme, a "vacuum-conditional beam-splitter", was posted 2026-07-24 by Ye et al. (AWS Center for Quantum Computing / Caltech) S[81]. Entangling is intended deterministic, gate time unmeasured; control is room-temperature microwave, bus connectivity.

The difficulty is geometric: a cat CNOT rotates the target's coherent amplitude through π conditioned on the control, briefly leaving the stabilised two-lobe manifold; any non-adiabatic drive term then leaks population between lobes as plain bit-flips, no longer exponentially suppressed in photon number. Dissipative schemes pin the state but pay in gate-induced phase-flips. The unitary scheme drops the dissipator and claims logical memory below 10⁻⁶ from a distance-7 repetition code of 13 cats — from assumed lifetimes and nonlinearity precision, not measurement S[81]. The floor is structural: one residual bias-breaking term turns the exponential into a polynomial and takes the qubit-count case with it S[95].

No cat–cat entangling gate exists in hardware as of 2026-09-04.

The neighbour shows the budget's shape: Ocelot's 2.8 µs cycle moved logical error only from 1.75(2)% at distance 3 to 1.65(3)% at distance 5, because per-CX phase-flip is already ~10⁻¹ D[80].

The <10⁻⁶ logical-memory claim in [81] rests on assumed component lifetimes and nonlinearity precision, with no independent replication and no measured gate as of 2026-09-04. The roadmap page [412] attaches the "13 minutes" bit-flip requirement to the Graphene chip without saying whether it holds idle or under a gate. No experimental group has reported an attempt at a cat–cat entangling gate.

No dedicated process: the gate reuses existing cavity bodies, junction lithography and room-temperature microwave stacks. Dropping the ancilla removes one transmon and readout chain per gate pair — Ocelot spends four ancillas on five cats — but adds a parametric tone per cat: lines per qubit are re-allocated, not reduced. At 10³ cats the wall is coax density and pump crosstalk in one dilution unit; at 10⁴–10⁶ it is the generic microwave wiring wall, no cryogenic-CMOS multiplexing of cat pump tones having been demonstrated.

On the superconducting bosonic (cat/GKP) architecture; requires two cat-encoded qubits and provides nothing downstream until it exists. It replaces the ancilla-mediated bosonic CX, trading a non-bias-preserving transmon channel for an unproven direct interaction; not switching leaves the ancilla's bit-flips setting the code floor. It does not move the derived clock, a 1.44 µs round here inside the measured 2.8 µs cycle, set by CX plus dispersive ancilla readout D[80]. Verification: the sole evidence is a proposal — no replication, no hardware attempt, and <10⁻⁶ is a code-level projection, not a measured fidelity S[81].

Money.
2025-01-28 · Alice & Bob · Series B · €100 M · — · closed fact
2026-05-22 · Alice & Bob · Series B extension · undisclosed · NVentures lead · closed C[88]
2026-06-17 · GENCI · buys first "Helium" · undisclosed · French HPC agency · closed C[87]
2025-11-06 · Nord Quantique · QBI Stage B · $5 M, up to $15 M · DARPA · announced G[65]

Market & supply chain. No supplier is specific to this gate; it reuses cat vendors' fabrication and pays for G3 alone.

IP & standards. No dated patent family specific to a bias-preserving cat–cat gate was found as of 2026-09-04.

Roadmaps & track record. AWS: promised 2026-07, no experimental date S[81]. Alice & Bob: promised on the live roadmap, for 2030 — Boson 4 (2024) and Helium (2026-06) landed, but every rung past Lithium (48 cats, 4 logical, 10⁻³) presumes this gate R[412].

Strategic reading. If measured, cat codes keep their qubit-count argument and surface-code transmon vendors lose; if still theory past 2028, dual-rail erasure takes the hardware-efficient slot.

Confirm by 2028 if a measured two-cat gate holds bit-flip time within 10× of idle; demote if 2028 passes with only ancilla-mediated gates, since the 2030 rung and the 126,133-cat class of estimates lose their premise S[95]. Best case 2029: bias above 10³ under drive. Worst case: cat logic runs through ancillas indefinitely. Open: does the scheme survive junction-nonlinearity spread; can the gate be characterised without ancilla contamination; who attempts hardware first? Watch Ocelot follow-ups and the Lithium chip.