Rotated surface code (+ yoked variants) code_surface

A CSS stabiliser code: weight-4 X and Z plaquettes on a square lattice, weight-2 on the boundary. The rotated layout — the one everybody builds — puts one logical qubit in d² data and d²−1 measure qubits: a distance-7 patch is 97 physical qubits. Errors show up as pairs of syndrome defects, which a decoder pairs across a three-dimensional matching graph (two space dimensions, d rounds) into a Pauli frame. Lineage: Kitaev's toric code (1997) S[649]; the planar memory and its threshold in Dennis, Kitaev, Landahl and Preskill (2002) S[650]; the rotated d²-qubit layout in Bombín and Martín-Delgado (2007) S[651]; lattice surgery in Horsman et al. (2011) S[652]; the engineering canon in Fowler et al. (2012) S[653]; yoking in Gidney et al. (2023) S[654].

Attributes from the technology graph (a affinity; b time; c readout; d mobility; e control @ placement; f error structure as the code sees it; g manufacturing): a = 0.5, carrier-agnostic — a layout, not a device, with b and c inherited from the host and e, g none of its own; d = static, patches moving only by lattice surgery; f = Pauli, the defining assumption and the defining weakness, since whatever is not an X/Z flip — leakage, loss, bias, erasure — is discarded information or unmodelled damage. Rank 7 of 111; shared by the superconducting, neutral-atom and spin families.

The code turns a physical error rate p into a logical rate falling exponentially in d, while p sits below a threshold. Λ, the factor by which logical error drops per two distance steps, is the whole economics: at Λ = 2.14 a tenfold drop in logical error costs three factors of Λ (log 10 / log 2.14 ≈ 3.0), so d grows by about 6 — from d=7 that is ~3.5× the qubits, since a patch needs 2d²−1. The threshold is decoder- and noise-dependent: 0.937% under uniform circuit-level depolarising noise S[8], but 0.55% for Riverlane's unweighted hardware decoder against 0.7% for weighted matching under leakage D[238]. Every quoted Λ describes a decoder as much as a chip.

Three floors are intrinsic. Area and time: a logical qubit is 2d²−1 physical qubits and a logical operation costs d rounds, so from 7.72×10⁻⁴ at d=7 with Λ ≈ 2 D[2], reaching 10⁻⁶ needs d ≈ 25 and over 1,200 physical per logical unless p falls below 10⁻³; at p = 10⁻³ the teraquop footprint (for 10¹² reliable operations) is about 1,500 physical per logical plain, 800 with one-dimensional and 600 with two-dimensional yokes S[654], or about 650 plain with correlated matching S[655]. Non-Pauli errors: leakage produces syndromes matching cannot explain, and atom loss is tractable only if the decoder is told where it happened. Correlated bursts: Google sees events roughly hourly pinning a floor near 10⁻¹⁰ irrespective of d D[1]. What moves the floor is error-structure engineering — bias, erasure, leakage removal — exactly what this code discards; yokes move only the constant.

Best demonstrated as of 3 Sep 2026: distance-7 memory at 7.72×10⁻⁴ logical error per cycle on Google's 105-qubit Willow, with reinforcement-learning calibration inside the QEC loop D[2]. Typical at scale: nothing. No vendor sells a surface-code logical qubit; logical two-qubit gates exist only at d=3 D[43]; on atoms the code ran on 448 atoms for four rounds D[4].

Dominant term: two-qubit gate error, about 40% of the comparable colour-code budget on the same chip D[41], then leakage and readout, then bursts no larger d removes D[1].

The code has no fabrication of its own; it imposes one — a static degree-4 lattice, a measure qubit between every data pair, non-destructive mid-circuit readout on every ancilla, and uniformity, because all 2d²−1 qubits must work. That is a yield problem in d², and why Google patented variants tolerating dead qubits G[656]. Its real supply chain is the decoding chain: Riverlane's decoder takes about 6% of a Xilinx VU19P's logic at d=17 D[238], and that FPGA family is single-source (AMD), as is the GPU alternative (NVIDIA, 3.84 µs round trip over NVQLink fact). Cost per logical qubit is unpublished. Export exposure: the US BIS rule of 2024-09-06 fact controls refrigerators (3A904), and quantum computers (4A906) only when their qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact; a distance-5 patch, 49 qubits, is caught only at a C-NOT error of 10⁻⁴ or better.

Every cycle measures and resets every ancilla: on Willow, 48 measurement bits per 1.1 µs for a distance-7 patch, roughly 44 Mbit/s of syndrome per logical qubit D[1]. The decoder must consume that stream faster than it arrives or the backlog diverges — sub-microsecond per round in FPGA fabric D[238] against Google's 63 µs mean latency at d=5 in 2024 D[1]. At 10³ qubits the wall is per-qubit wiring; at 10⁴ it is syndrome bandwidth off the fridge, the case for cold-stage predecoding (a cryo-CMOS study claims 3,780× reduction under 0.56 mW at 4 K Sfact); at 10⁶ decoding is a datacentre-scale streaming problem sized by syndrome rate, not qubit count.

Five architectures carry it: superconducting transmons, alkali neutral atoms, alkaline-earth(-like) erasure-native atoms, silicon/germanium quantum-dot spins and donor spins in silicon. It requires only a static nearest-neighbour lattice — the reason it is the default — hosts magic-state factories (cultivation reaches 0.9999(1) at 8% acceptance D[42]) and feeds FPGA and neural decoders D[238], [657]. It is replaced by, not composed with, the colour code (better gates, worse slope: Λ₃/₅ = 1.56 on the same chip D[41]), bivariate bicycle qLDPC codes (288 physical for 12 logical against roughly 3,000 surface-code qubits D[248]) and high-rate transversal codes on movable atoms. It conflicts with cat qubits (an unbiased code wastes the bias), dual-rail encodings (matching discards erasure flags) and destructive detection. Switching costs run both ways: leaving buys a 3–10× overhead cut and demands connectivity the hardware lacks; staying costs 600–1,500 physical per logical S[654]. It is the one genuinely platform-agnostic code-layer node, which is why a decoder company can exist. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 0.65 µs derived on the transmon lattice against the measured 1.1 µs cycle, readout and reset two-thirds of it rather than the 25–40 ns gates D[1]; 1.31 ms on atoms, set by transport. Neighbouring empty slots: a decoder inside the fridge, and cross-module patches — no code has run across two modules.

Λ is a fit of logical error per cycle against d, and three things make it soft. Decoder-conditioned: the same Sycamore data gives 3.028% under tensor-network decoding and 2.901% under AlphaQubit at d=3 D[602], [657]. Subset-conditioned: a d=7 patch adds worse qubits to the d=5 set. Duration-conditioned: four-round circuits D[4] never see the drift and burst physics a 10⁶-cycle run does D[1]. Not captured: leakage populations, bursts, reload survival bias, decoder failure in real time. Replicated independently — Google D[1], [2], USTC D[3], Harvard/MIT/QuEra D[4].

Conflicts. Λ per two distance steps: 2.14 ± 0.02 (Google, d=3→7) D[1] versus 1.40(6) (USTC) D[3] versus 2.14(13)× (atoms, four rounds, lost on reloading) D[4] — different noise, not different codes, and only Google's survives a million cycles. Threshold: 0.937% S[8] versus 0.55–0.7% under leakage D[238]; budget against the second.

Riverlane's Series C is $75 M in the 2024-08-06 release C[661] but "$85 million in 2024", with "$120 million+" cumulative, in the 2026-03-12 roadmap release C[658]. The yoked-code footprints (≈1,500 / ≈800 / ≈600 physical per logical at p = 10⁻³) come from a secondary rendering of arXiv:2312.04522 S[654]. Not published: the cost or energy per logical qubit, and Riverlane's revenue and contract values.

Money. Nobody funds a code; these are deliverables denominated in surface-code units.

• 2024-05-01 · Riverlane · Horizon Europe EIC Transition grant (SkyTALE, with Qblox) · £2.1 M · awarded C[660]
• 2024-08-06 · Riverlane · Series C · $75 M · Planet First Partners lead, with ETF Partners, EDBI, Cambridge Innovation Capital, Amadeus · closed C[661]
• 2025-11-06 · DARPA · QBI Stage B · up to $15 M each, eleven teams; IBM the only transmon vendor, its plan qLDPC fact
• 2026-03-12 · Riverlane · roadmap release claims $120 M+ raised and an "$85 M" Series C · conflicts with the 2024 release C[658]
• 2026-06-02 · IBM · quantum commitment · >$10 B over five years · announced fact

Market & supply chain. The only sellable artefact here is the decoder and its integration; Riverlane is the sole pure-play, claiming over 20 partnerships with makers and national labs C[658]; NVIDIA commoditises the GPU path. Concentration risk is upstream (AMD/Xilinx, NVIDIA, a two-vendor refrigerator market); unit economics are unpublished beyond the 600–1,500 physical per logical every buyer pays S[654]. Only G3 and G4 pay for it.

IP & standards. Google LLC, US 12,518,194, "Surface codes with densely packed gauge operators" (granted 2026-01-06) G[656]; Riverlane Ltd, GB 2641501 A, "Quantum decoder" (published 2025-12-10) G[662]. The code is unpatentable prior art from 1997–2007 S[649], [651], so the fight is over decoders and layouts. No standard; the interfaces are open source — Stim, PyMatching, Deltakit P[397].

Roadmaps & track record.

• Google: promised 2023-02 · milestone 3, a "long-lived logical qubit" at 10⁻⁶ · not reached; best 7.72×10⁻⁴ at d=7 D[2] C[32].
• IBM: promised 2025-06-10 · Kookaburra, first qLDPC memory-plus-logic module, in 2026 · not delivered as of 2026-09-03 fact.
• Riverlane: promised 2026-03-12 · megaquop before end of decade, gigaquop early 2030s, teraquop from 2033 · pending C[658].
  Credibility: Google delivered every milestone it announced, late but real, and alone has numbers surviving a million cycles; IBM executes but has left this code; Riverlane ships peer-reviewed hardware; the atom camp has the best overhead story and the weakest duration data fact.

Strategic reading. If the surface code stays the workhorse the winners are whoever makes physical qubits cheap and cycles fast — the superconducting camp — plus a decoder supply chain selling to every platform. The losers are anyone whose case assumed 10² physical per logical: at 600–1,500, a 200-logical-qubit machine is a 10⁵-qubit machine — IBM's stated reason for leaving D[248]. Substitution threats are dated: qLDPC at break-even on trapped ions, transversal codes on movable atoms, erasure-adapted codes. Bargaining power sits with platform vendors, except in real-time decoding, which most would rather buy than build.

Confirm within 12–24 months if: any group reports Λ ≥ 3 over ≥10⁵ cycles; a logical two-qubit gate at d ≥ 5 reaches 99% without post-selection; a patch runs across two modules; yoked patches appear on hardware. Demote if a qLDPC memory beats a surface-code patch at equal qubit count before end-2027. Best case by 2029: a few hundred logical qubits at 10⁻⁶ on 10⁵–10⁶ physical qubits, decoding a commodity — what Starling and Libra assume. Worst case: Λ stays near 2, d ≈ 25 stays the price of 10⁻⁶, and the code survives only as a benchmark. Open questions: (1) does Λ hold above 10³ physical qubits, where crosstalk and drift scale differently? (2) can yoking run on hardware, or does outer-code decoding defeat the real-time budget? (3) how much of the 2026 record is calibration rather than physics, given that RL steering alone moved d=7 from 1.43×10⁻³ to 7.72×10⁻⁴? Watch: Google's next distance step and IBM's Kookaburra.

Lattice surgery split across two processors joined by a photonic link does not automatically keep distance d at the seam: a straight Bell-pair interface gives d + 1 on the merge outcome but only ⌊(d + 1)/2⌋ on the perpendicular observable, a zig-zag partition restores d, and a linear-cluster fusion seam gives 2d + 1 and d — distances that count interface faults only P[893].