Zuchongzhi 2.1
USTC / Hefei National Laboratory
Zuchongzhi 2.1
Register profile — the machine's variant of its architecture
qubit type: tunable transmon
gate mechanism: tunable coupler
connectivity: square lattice
control: room-temperature RF
control placement: room-temp
readout: dispersive
gate evidence: a published figure (source class not yet tagged)
codes: surface-17
flags: claim later eroded, second hand numbers, source not confirmed
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to |2⟩ is the price. |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▣ Fig. 1b (qubit, coupler and readout circuit schematic); Fig. 2c (Pauli error of 99 2Q gates) ✅ tunable coupler (110 couplers); 2Q ≈97–98% (era-typical, second-hand) |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▣ Fig. 1a (11x6 lattice, 110 couplers); Fig. 3a (topology diagram, 60 used qubits) ✅ square lattice, degree 4; 11×6 array with 110 tunable couplers |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▣ Fig. 1a (second chip carries all control lines) ✅ room-temperature RF |
| 6 Readout | Dispersive microwave readout (+TWPA, Purcell) · primary ▣ Fig. 1b (readout circuit schematic); Fig. 2a (readout error of 60 qubits) ✅ dispersive |
| 7 Code | Rotated surface code (+ yoked variants) · primary ▤ abstract; results ✅ d=3 CSS surface code (17 of 66 qubits), up to 11 cycles, MWPM decoding (sweep 7 Oct 2026, source read) |
| 8 Decoder | |
| 9 Interconnect | — none — nothing in this layer ▣ Fig. 1a (single flip-chip module: qubit chip + control-line chip; no inter-module link) ✅ monolithic single module, no interconnect |
| 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▣ Fig. 1a (two sapphire chips combined by flip-chip technique) ✅ |
evidence: ✅ 8 / 10
Pictures
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