IBM Quantum Nighthawk r2
IBM Quantum Nighthawk r2
Register profile — the machine's variant of its architecture
qubit type: fixed-frequency transmon + next-gen tunable coupler
gate mechanism: native CZ
connectivity: square lattice, degree 4
control: room-temperature RF; per-qubit high-dynamic-range coupler to a cold bath for reset
control placement: room-temp
readout: multiplexed dispersive; effective T1 pulled from ~200 us to ~25 ns on demand, init error /25
gate evidence: the vendor's datasheet or dashboard
codes: rotated_surface
flags: conflicting claims
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 bare transmon two-level subspace; no encoding beyond the physical qubit |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▤ § IBM Quantum Nighthawk r2—more circuits faster ✅ native CZ via 218 next-generation tunable couplers, "Heron-class gate fidelity"; 7,500+ gates with accurate observable estimation (Aug 2026) |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▤ § IBM Quantum Nighthawk r2—more circuits faster ✅ square lattice, degree 4 (first departure from heavy-hex since 2021) |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▤ § Accelerating computations with independent, high-speed qubit reset ✅ room-temperature RF; each qubit has a high-dynamic-range tunable coupler to a cold dissipative bath for on-demand reset |
| 6 Readout | Fast unconditional / dissipative qubit reset · primary ▤ § Accelerating computations with independent, high-speed qubit reset ✅ dissipative reset via 120 dedicated reset elements: effective T1 ~200 µs → ~25 ns on demand, idle ~1 µs, init error ÷25, neighbours undegraded (Aug 2026) Dispersive microwave readout (+TWPA, Purcell) · alternate ▨ ✅ multiplexed dispersive readout, paired with on-demand dissipative reset (effective T1 ~25 ns, init error ÷25) |
| 7 Code | Rotated surface code (+ yoked variants) · primary ▤ Fig. 2c; methods 🔎 d=3 surface-code memory, up to 10 rounds, on 11 patches of ibm_phoenix (sweep 7 Oct 2026, source read) Error mitigation in the code slot (ZNE, PEC) — not a code · alternate ▤ § Quantum advantage and other early results on Nighthawk r2 ✅ no code; code slot occupied by error mitigation: 7,500+ gates with accurate observable estimation (Aug 2026) |
| 8 Decoder | |
| 9 Interconnect | Multi-chip modules / l-couplers (same cryostat) · alternate ▥ 🔎 planned: up to three 120-q modules (360 q) in 2026, not announced as delivered; ≥1,000 q via l-couplers 2027; ~1,080 q (9×120) in 2028 — none — nothing in this layer ◌ 🔎 monolithic single 120-qubit module, no interconnect; 3-module config planned |
| 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▨ 🔎 IBM Albany 300 mm superconducting-qubit fab (IBM claims 50% shorter processor development, 10× complexity headroom vs 200 mm) |
Standard records
2Q layers per syndrome round → 7500 gates · best (2Q gates with accurate observable estimation)
Aug 2026 · source
reset error → 0.04 · best (initialisation error divided by 25; absolute not published)
relative figure only · Aug 2026 · source
T2 coherence (echo/DD) → 27 µs · typical (median effective as delivered)
1.6e-4 s with software crosstalk suppression · Mar 2026 · source
reset / initialisation time → 25 ns · best (effective T1 on demand)
high-dynamic-range coupler to a cold bath · Aug 2026 · source
evidence: ✅ 7 / 13