Erasure-adapted codes code_erasure

An erasure-adapted code is a stabiliser code whose decoder takes, besides the syndrome, a per-qubit flag saying "this qubit was lost or left the code space here", with layout and schedule chosen for a channel in which located errors dominate. A located error removes the which question and leaves only the what, so the surface code fails only when erasures percolate — a 50% code-capacity threshold set by square-lattice bond percolation S[679], against 18.9(3)% for depolarising noise S[334] — and its distance against erasures is d rather than ⌈d/2⌉. Maximum-likelihood erasure decoding is linear-time peeling on a spanning forest S[680]; Union-Find extends it to Pauli errors in O(n α(n)) S[681]. The hardware turn came in 2022: 98% of ¹⁷¹Yb errors convertible, lifting the circuit-level surface-code threshold from 0.937% to 4.15% S[8], and dual-rail transmons, where at 1% erasure the code tolerates 0.51% Pauli error, 5.2× the standard figure S[334]; the first full loss-correction cycle had run on five trapped ions in 2020 D[682]. The flags belong to the Mid-circuit erasure check brief (layer 6); this brief covers what the code does with them.

Attributes (graph record; legend: a affinity natural↔fabricated; b time, deterministic/heralded entangling; c readout; d mobility; e control @ placement; f error structure; g manufacturing):

• a = 0.5 — carrier-agnostic; one decoder serves atoms and transmons.
• b = no time or entangling of its own.
• c = none — it consumes the check's flag.
• d = static.
• e = no control modality, no placement.
• f = erasure — located loss dominant, small Pauli residual.
• g = none — layout and software.
  Rank 3 of 111; shared by the neutral-atom and superconducting families; it pairs a fabricated carrier with an erasure error structure.

The gain has three parts, each taxed. Threshold: the converted fraction sets it. Wu's 4.15% assumes 98% conversion S[8]; measured fractions are 56(4)% of single-qubit and ≈33% of two-qubit errors on ¹⁷¹Yb D[141] and 38(6)% of Princeton's CZ error D[142], so the realised threshold sits between the Pauli and erasure limits; biased-erasure XZZX codes lift the ceiling to 8.2%, hybrid-fusion to 10.3% S[643]. Checks are not free: each exposes the qubit to T1, and erasure qubits win only when the check is short against the cycle S[683]; with false positives and negatives the threshold stays at least twice the Pauli value and the effective distance roughly doubled S[395]. Erasures spread through gates, and a missed erasure re-enters as leakage, the error the surface code handles worst S[684]. The idealised ceiling is Quantum Circuits' simulation: ancilla erasure 0.4%, data erasure 0.1%, dephasing 0.04/0.01/0.01% and perfect checks delayed to the end of each round give Λ ≈ 27 per distance step against Λ ≈ 14 for 0.1% depolarising noise S[84]; Google's hardware surface code sits at Λ = 2.14(2) D[1]. The bias behind such numbers is ≈40:1 — 6×10⁻³ erasure against 1.6×10⁻⁴ Pauli per operation S[334] — matching AWS's measured 42(1) D[85] fact. What moves the floor: conversion under two-qubit gates, the false-negative rate, check time, and decoders that use delayed loss information so no mid-circuit check is needed S[508].

Best demonstrated, atoms: Harvard/MIT/QuEra's surface code on up to 448 atoms, 2.14(13)× below threshold in a four-round characterisation circuit, loss information plus machine-learning decoding giving 1.73(13)× over conventional decoding D[4]; Princeton's [[4,2,2]] block, whose logical decay slows 1.9(4)× with erasure flags in the decoder D[142]; Microsoft/Atom Computing's 24 logical qubits in 48 atoms with 1.8 lost atoms corrected per run D[149]. Superconductors: no erasure-decoded code has run on dual-rail hardware as of 3 Sep 2026; the largest erasure-encoded circuits are SUSTech's four dual-rail transmons, with a 93.9% three-logical-qubit GHZ state (Nature Physics version) D[406] fact and Quantum Circuits' 8-qubit Seeker, error-detecting only C[86] fact. Typical at scale: only the Harvard and Microsoft machines decode with loss flags above 100 atoms.

Dominant error term today: on atoms the unconverted two-qubit error, ≈62–67% of CZ error D[141], [142]; on dual-rail the ancilla's erasure per CZ, 0.400(4)%, and check dead time D[84] fact; on both, a false-negative tail nobody has counted over many rounds.

Nothing is fabricated for the code; its burden lands on the hardware it selects. Dual-rail asks for two good transmons or two cavities per site — a yield-squared problem — plus an ancilla per cavity pair S[399], hence Quantum Circuits' hand-assembled 8 → 17 → 49 → 181 plan R[94] fact. Alkaline-earth(-like) atoms add no hardware but cost single-qubit fidelity in the metastable manifold, 99.12(4)% against 99.968(3)% in the ground state of JILA's device D[645]. The decoder is the code's only artefact: Union-Find on a Xilinx VCU129 decodes d=21 at 11.5 ns per round under 0.1% phenomenological noise D[685]; erasure input is native to Union-Find S[681] but no FPGA benchmark with erasure flags is published; Stim exposes HERALDED_ERASE P[397]. Unit cost: 2× physical qubits per site on dual-rail, against Quantum Circuits' claim of 10–20 physical per logical instead of ≈200 C[86]. Export control: the BIS rule of 2024-09-06 G[301] fact controls quantum computers (4A906: only when qubit count and C-NOT error fall in the same band, from 34–99 qubits at ≤ 10⁻⁴ to any error from 2,000 qubits fact), software "specially designed" for developing or producing controlled qubit and control devices (4D906) and the related technology (4E906); a decoder shipped as firmware for a controlled control system falls inside 4D906.

The code adds one bit per qubit per cycle to the syndrome stream and a decision: reset and re-entangle the erased qubit before the next round, or defer. On dual-rail that is feed-forward within ≈1 µs (0.50 µs gate, 0.38 µs check) D[84], [85]; on atoms a camera frame and a reload, ≈1 ms D[4]. Delayed-erasure decoding S[508] and superchecks D[4] remove the mid-circuit branch at the price of correlated decoding. Walls: at 10³ the wall is the hardware's; at 10⁴ the decoder must absorb ≈10⁴ flags plus syndromes per microsecond — 10 Gbit/s, within FPGA reach D[685] but untested with erasures; at 10⁶ dual-rail means 2×10⁶ transmons, and on atoms the frame budget of the Mid-circuit erasure check brief applies unchanged.

Two architectures: superconducting dual-rail erasure (D-Wave/Quantum Circuits, AWS, SUSTech) and alkaline-earth(-like) neutral atoms (Atom Computing/Microsoft, Princeton, Caltech). The code requires the mid-circuit erasure check's flags, provides logical qubits to nothing yet registered downstream, and replaces the Pauli-decoded surface code. The price of switching is hardware, not software: 2× physical qubits and a check per cycle on dual-rail, the metastable fidelity tax on atoms, plus a decoder that weights erased edges to zero. It conflicts with nothing formally but competes with IBM's qLDPC memory for the same G4 budget Rfact. The atom and superconducting camps share one artefact, the decoder. A fabricated carrier with an erasure error structure is genuine on dual-rail; atoms bring erasure as a natural carrier. Derived clock = sum of the syndrome round: gate layers + transport + readout + reset for the architecture: 2.8 µs on dual-rail (gate-limited, four 0.5 µs layers over the 0.40 µs check), 1.3 ms on atoms (transport); the code rides on the host code's d₂ and adds no term. Neighbouring slots: erasure-adapted qLDPC codes (no demonstration found), the cold-stage decoder, and, one column over, photonic fusion-based computation at 10.4% tolerated loss per fusion S[179], where Xanadu reports loss 24.1× above threshold in 2026 Rfact.

Headline numbers are logical decay rates versus hold time decoded with and without flags (Princeton) D[142], or detected-error ratios between distances in a four-round circuit (Harvard's 2.14(13)×) D[4]; simulated Λ comes from Stim-style circuit noise with an assumed bias S[84]. Not captured: post-selection — Princeton's teleportation fidelities, 0.771(9) → 0.802(8), are conditioned on trivial syndromes and a flag D[142]; four rounds are not a memory over 10⁵ rounds; the Λ ≈ 27 simulation assumes perfect checks, no false negatives, no check-induced dephasing S[84]; nobody reports survival beside Λ. Independent replications: Harvard/QuEra D[4], Microsoft/Atom D[149], Princeton D[142]; theory from AWS S[334], [683], [684], Yale S[395], [643], Duke S[392]. Conflicts: (i) the [[4,2,2]] gain is 1.9(4)× in arXiv v1 and v2 (2026-06-23) D[142] but 3.6× in the technology graph from the Nature Physics text D[142] fact; the published text is paywalled and 1.9(4)× is used. (ii) 98% conversion S[8] against 38–56% measured D[141], [142]. (iii) Λ ≈ 27 S[84] against Λ = 2.14(2) on the best Pauli-decoded hardware D[1] — a simulation-to-hardware gap.

Gu, Retzker and Kubica publish thresholds as surfaces, not single values S[684]. The 11.5 ns per decoding round is for phenomenological noise D[685]. Not published: an FPGA decoding benchmark with erasure flags; a Princeton or Harvard patent family on erasure conversion; the neutral-atom species of planqc and of Google; the cost or energy per logical qubit, from any actor; and the NSF award behind D-Wave's "$1.57 million in NSF funding for gate-model development" C[15].

Money.

• 2024-08-15 · Quantum Circuits · Series B close · >$60 M · ARCH, F-Prime, Sequoia, Hither Creek · ≈$84 M cumulative per trade press · closed fact
• 2025-11-04 · US DOE · NQISRC renewal, C2QA (Brookhaven/Yale) · $125 M of $625 M over up to five years · programme · awarded G[474], [686]
• 2025-11-06 · DARPA QBI Stage B · up to $15 M each · Atom Computing, QuEra among eleven; no dual-rail vendor · official G[65] fact
• 2026-01-07 · D-Wave · acquires Quantum Circuits · $550 M ($300 M stock + $250 M cash) · closed 2026-01-19/20 C[14] fact
• 2026-05-21 · D-Wave; Atom Computing · US DoC CHIPS letters of intent · $100 M each · LOI fact
• 2026-06-16 · Atom Computing · Series C · $100 M · Third Point · >$300 M cumulative · closed fact
• 2026-08-06 · D-Wave · Q2-2026 results · revenue $3.1 M, cash $546.2 M; $1.57 M NSF grant for gate-model work · reported C[15] fact

Market & supply chain. Nobody sells an erasure-adapted code; the decoders are open-source (Stim, PyMatching, Union-Find) P[397] and the FPGA implementations academic D[685], so the money is in the hardware overhead: two transmons or two cavities plus an ancilla per site, or a metastable manifold and a camera. Concentration risk is the dual-rail readout chain and refrigerators, BIS-listed G[301]; on atoms, the ¹⁷¹Yb/⁸⁸Sr laser set. G3 and G4 buy the full code; G2 and G1 pay today for erasure detection as post-selection (Seeker C[86], Caltech's excised Rydberg simulator D[143]); G5–G7 do not pay.

IP & standards. Amazon Technologies US 11,748,652 B1, heralded amplitude-damping decay for QEC (Kubica, Retzker; granted 2023-09-05) G[336] fact; Yale US 12,288,135, asymmetric-error-channel ancilla (granted 2025-04-29) G[408]; Quantum Circuits' cavity families sit with D-Wave. No Princeton or Harvard erasure patent surfaced in the searches run; no database count found. No standard; Stim's HERALDED_ERASE P[397] is the de-facto interface; D-Wave announced a forthcoming gate-model simulator for "error-aware programming" C[15].

Roadmaps & track record.

• D-Wave: promised 2026-01-07 · first dual-rail system in 2026 · not delivered as of 2026-09-03; restated 2026-08-06 as a 17-qubit system with logical error 2× below physical in 2026 C[14], [15].
• D-Wave: promised 2026-06-01 · 49 qubits / 20× (2027), 181 / 2,000× (2028), 10 logical (2030), 100 logical (2032), Λ = 10 · pending R[94] fact.
• QuEra: promised 2024-01 · 100 logical qubits in 2026 · missed; restated 2026-06-15 as Libra, >256 logical at 10⁻⁶ in 2028 R[162] fact.
• Atom Computing/Microsoft: promised 2025-07-17 · Magne, 50 logical qubits, delivery around the turn of 2026/27 · pending fact.
  Credibility: Quantum Circuits/D-Wave publish the physics and miss the dates; Harvard/QuEra deliver papers on schedule, roadmaps late; Microsoft/Atom on schedule, silent on the code; AWS publishes and promises nothing; Princeton delivers each step of its 2022 proposal S[8], smaller than promised.

Strategic reading. If erasure-adapted codes reach Λ ≥ 5 on hardware, the winners own erasure-native qubits at scale — D-Wave's cavity line, AWS's transmon pairs, the ¹⁷¹Yb camp (Atom Computing, Google's atom track) — and the decoder becomes a commodity; the losers are Pauli-only roadmaps buying Λ with fidelity alone (Google's superconducting line, IBM's qLDPC) and rubidium vendors without a metastable manifold. Substitution runs both ways: delayed-erasure decoding S[508] and superchecks D[4] give atoms most of the gain without erasure-native qubits; qutrit erasure encodings would strip the 2× overhead from transmons. Bargaining power sits with platform vendors; decoder authors have none.

Confirm within 12–24 months if: any group decodes a d=3 → 5 memory with erasure flags over ≥ 10 rounds and reports Λ ≥ 3 with survival; D-Wave's 17-qubit system shows logical error 2× below physical by mid-2027 C[15]; a dual-rail simulation with measured false negatives and check dephasing still returns Λ ≥ 10; atom conversion under two-qubit gates passes 70%. Demote if end-2027 arrives with erasure decoding worth < 2× on every platform. Best case by 2029: dual-rail memories at Λ ≈ 5–10 with 100–200 qubits and Yb machines running loss-aware codes by default. Worst case: a decoder option worth 1.7–1.9× while Pauli-decoded transmons reach Λ ≈ 3–4 without it.

Open questions: (1) what is Λ once false negatives accumulate as leakage over 10³ rounds? (2) does the 40:1 bias survive parallel gates on shared readout lines? (3) can the metastable fidelity tax on Yb be removed? (4) is an erasure-adapted qLDPC code with a fast decoder possible? Watch: D-Wave's 2026 delivery, AWS's next multi-qubit paper, Google/Kaufman's Yb results.

Erasure-aware decoding also works at a photonic interface between surface-code processors: with ideal local operations, the threshold for erased fusion outcomes reaches the 50% bond-percolation ceiling of the square lattice (fitted 49.40–50.60% at d = 11–19), equivalent to 18.35% photon loss without fusion boosting, and it falls roughly linearly with resource-state error and ever faster as local circuit noise nears its own threshold P[893]. The result is from simulation only.