D-Wave gate-model dual-rail system
D-Wave gate-model dual-rail system
Register profile — the machine's variant of its architecture
qubit type: dual-rail cavity qubit
gate mechanism: bosonic CZ
connectivity: planar
control: room-temperature control plus on-chip flux-DAC multiplexing carried over from the annealer line
control placement: room-temp + flux-DAC
readout: erasure-flagged readout
gate evidence: a published figure (source class not yet tagged)
codes: dual_rail
flags: no code named, a target, not a device
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Bosonic cavity mode · primary ▣ Fig. 1a (device hardware schematic: pair of 3D λ/4 coaxial cavities per qubit, 3 SQUID transmon couplers) ✅ dual-rail cavity qubits; 17 physical qubits targeted 2026 (49 in 2027, 181 in 2028); not shipped as of 15 Sep 2026 |
| 2 Encoding | Dual-rail (erasure) encoding · primary ▣ Fig. 1a (dual-rail erasure qubit in a pair of cavities); Abstract ✅ dual-rail erasure encoding; 21-q gate-model simulator with dual-rail error detection shipped 18 Jun 2026 |
| 3 Gate mechanism | Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) · primary ▣ Fig. 1b (Swap-Wait-Swap CZ sequence); §The SWS CZ gate; Fig. 2 (gate benchmarking) ✅ bosonic CZ (register); quoted 99.9 % 2Q figure is error-detected / post-selected, not unconditional |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▨ 🔎 planar layout (register); no topology detail published |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▨ 🔎 room-temperature control plus on-chip flux-DAC multiplexing carried over from the annealer line On-chip flux-DAC multiplexing · alternate ▨ 🔎 on-chip flux-DAC multiplexing, annealer heritage applied to gate-model control (cross-path: ct_fluxdac filed on anneal only) |
| 6 Readout | Mid-circuit erasure check · primary ▣ Fig. 1a (transmon + readout resonator per cavity); main text: end-of-line erasure-detected measurement ✅ erasure-flagged readout via dual-rail error detection; no measured readout figures (all targets) |
| 7 Code | Erasure-adapted codes · primary ▨ release text 🔎 D-Wave describes its gate-model line as dual-rail; no outer code named (sweep 7 Oct 2026, source read) |
| 8 Decoder | |
| 9 Interconnect | Multi-chip modules / l-couplers (same cryostat) · primary ◌ 🔎 multi-chip module technology per note; no D-Wave module or coupler detail published |
| 10 Manufacturing | 3D machined superconducting cavities · primary ◌ Fig. 1a (pair of 3D λ/4 coaxial cavities per qubit; the fabrication route is inferred) 🔎 3-D superconducting cavities: a pair of λ/4 coaxial cavities per dual-rail qubit; body material and machining not published Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · alternate ◌ Fig. 1a (three SQUID transmon couplers; transmon and readout resonator per cavity) 🔎 Josephson-junction lithography for the three SQUID transmon couplers and the ancilla transmons; no fab process published |
evidence: ✅ 4 / 12