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SUSTech biased-erasure cavity qubit

Southern University of Science and Technology

SUSTech biased-erasure cavity qubit

Southern University of Science and Technology · superconducting circuits · DEMONSTRATED (29 Jan 2026) · 1 physical qubits · access: lab-only

Register profile — the machine's variant of its architecture

qubit type: vacuum + two-photon encoding in a cavity giving a biased erasure qubit; erasure bias >265
gate mechanism: bosonic gates; benchmarked logical gate error 0.29%
connectivity: single mode
control: room-temperature control
control placement: room-temp
readout: leakage-to-erasure conversion >99.3%; assignment error <1%
gate evidence: no published figure
codes: fock_0n

Technologies by layer — the machine's cell per layer

1 Qubit carrier
Bosonic cavity mode · primary ▣ Fig. 1b (cavity coaxial stub, transmon ancilla, readout resonator); SI §I.A ✅
vacuum + two-photon encoding in a cavity → biased erasure qubit; erasure bias >265; logical T1 6.2 ms, T2 3.1 ms (Jan 2026)
2 Encoding
— (Atlas gap: ∅G-fock02) · primary ▣ Fig. 1c,d (|0_L⟩=|0⟩, |1_L⟩=|2⟩ level diagram; logical Bloch sphere/Wigner) ✅
qubit in |0⟩/|2⟩ Fock states of one cavity; photon loss flagged as erasure
3 Gate mechanism
Ancilla-mediated bosonic gates (cat CX, dual-rail CZ, beamsplitter) · primary ▣ Fig. 4 (logical RB, residual error 2.86e-3/gate); Fig. S9 (X_L/2 process matrix); SI §IV ✅
bosonic gates; benchmarked logical gate error 0.29% (Jan 2026)
4 Connectivity / transport
Static nearest-neighbour lattice · primary ▤ 🔎
single cavity mode; no qubit–qubit connectivity (degree 0)
5 Control
Room-temperature electronics + per-qubit coax/flex · primary ▣ Fig. S1 (measurement setup: HDAWG/UHFQA electronics, JPA chain, microwave routing); SI §I.A ✅
room-temperature control
6 Readout
Mid-circuit erasure check · primary ▣ Fig. 2a–d (cascaded parity measurement, erasure detection error map); Methods: Mid-circuit erasure detection ✅
leakage-to-erasure conversion >99.3%; assignment error <1% (Jan 2026)
7 Code
Erasure-adapted codes · primary ▣ Fig. 1a (XZZX surface code with biased-erasure data qubits, scheme); Fig. 3 (logical T1/T2) ✅
erasure-qubit code (dual_rail family) not run; single biased-erasure qubit with ~6.0× coherence gain vs break-even (Jan 2026)
8 Decoder
— none — nothing in this layer ▤ 🔎
no decoder (no code run)
9 Interconnect
— none — nothing in this layer ◌ 🔎
single-cavity device, no interconnect
10 Manufacturing
3D machined superconducting cavities · primary ▤ SI §I.A Experimental device and setup ✅
3D machined superconducting cavities — Machined aluminium cavities reach Q > 0.5×10⁹ (10 ms photon lifetime, Yale 2013); niobium accelerator cavities with no qubit attached hold photons for 0.5–2 s at ~10 mK (Fermilab 2020); cm-scale footprint per qubit — the scaling liability of cavity-based bosonic codes.

Standard records

QND fidelity / survival → 0.993 · best (leakage-to-erasure conversion)
Jan 2026 · source
T1 relaxation → 6.2 ms · best-of-line (logical)
Jan 2026 · source
T2 coherence (echo/DD) → 3.1 ms · best-of-line (logical)
Jan 2026 · source
evidence: ✅ 7 / 10