IQM Halocene
IQM Halocene
Register profile — the machine's variant of its architecture
qubit type: tunable transmon
gate mechanism: tunable couplers, native CZ; the QEC work assumes nearest-neighbour iSWAP
connectivity: Crystal grid; Constellation for QEC
control: room-temperature RF; modular decoder architecture with NVQLink
control placement: room-temp
readout: dispersive
gate evidence: a published figure (source class not yet tagged)
decoder mode: planned — named in a roadmap only
codes: rotated_surface, triangular_color
flags: schedule risk
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 bare transmon two-level subspace; no encoding beyond the physical qubit |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▣ Fig. 3 (nearest-neighbour directional layers); §III ✅ tunable couplers, native CZ; targets 99.7% physical 2Q at 150 q; tile-code QEC work assumes nearest-neighbour iSWAP |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▣ Fig. 3 (NN directional layers, square grid); §III ✅ Crystal square lattice, degree 4; Constellation (2-D lattice of Star cells) intended for scalable QEC — (Atlas gap: ∅G-bus) · alternate ▥ ✅ Constellation option: Star cells, each a central computational resonator giving all-to-all within the cell |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▥ 🔎 room-temperature RF control; modular decoder architecture with NVIDIA NVQLink |
| 6 Readout | Dispersive microwave readout (+TWPA, Purcell) · primary ◌ 🔎 multiplexed dispersive readout (IQM); 240 ns at 99.94% is a 2-qubit test chip, not this system |
| 7 Code | Rotated surface code (+ yoked variants) · primary ▨ article text 🔎 IQM plans up to 9 logical qubits with d=3 surface or colour codes on the Halocene line (2029) (sweep 7 Oct 2026, source read) Colour code (transversal Cliffords) · alternate ▨ article text 🔎 IQM names a d=3 colour code as the alternative to the surface code for the LUMI-IQ logical qubits (sweep 7 Oct 2026, source read) Non-local qLDPC codes (bivariate bicycle, 'gross') · alternate ▣ Fig. 1 (planar directional tile codes); Fig. 2 (vs surface); §II, §IV ✅ directional tile + barbell qLDPC codes with only NN iSWAP on a planar grid; ≈30 circuit qubits per logical, e.g. [[323,14,15]]; numerics only (Jun 2026) |
| 8 Decoder | GPU decoding via NVQLink · alternate ▨ ✅ planned GPU decoding over NVIDIA NVQLink; real-time QEC demonstrator (20 q + Zurich Instruments ZQCS + NVQLink) <4 µs end-to-end (Mar 2026) — none — nothing in this layer ▨ ✅ no decoder deployed; real-time correction planned for the 2028 LUMI-IQ upgrade |
| 9 Interconnect | |
| 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ◌ 🔎 superconducting-qubit lithography (IQM); no machine-specific fab source |
Standard records
code rate k/n → 30 circuit qubits per logical qubit · best layouts (directional tile codes, theory)
Jun 2026 · source
evidence: ✅ 7 / 14