Non-local qLDPC codes (bivariate bicycle, 'gross') code_qldpc

A bivariate bicycle (BB) code is a CSS stabiliser code whose two parity-check matrices are polynomials in a pair of commuting cyclic shifts, so the checks tile a torus: every check touches six qubits, every qubit sits in six checks. Four neighbours are near, two are long-range wraps — sparsity and high rate bought with non-planar connectivity. The lineage runs from MacKay's bicycle codes and Tillich–Zémor hypergraph products through Panteleev–Kalachev lifted products to Bravyi, Cross, Gambetta, Maslov, Rall and Yoder, Nature 627, 778 (2024-03-27), whose [[144,12,12]] "gross code" holds 12 logical in 288 physical qubits at a circuit-level threshold of 0.8%, against ≈3,000 physical for the same 12 logical in the surface code at p = 0.1% D[248].

Attributes (technology graph): carrier affinity 0.5 — a code layer, indifferent between natural and fabricated carriers but inheriting their errors. Characteristic time: none of its own; entangling neither deterministic nor heralded here. Readout: none of its own — it consumes fast non-destructive mid-circuit syndrome measurement from the carrier. Mobility: long-range, the defining requirement. Control modality: none, at no placement. Error structure as the code sees it: Pauli. Manufacturing: none.

The code sets no energy scale, only an accounting rate: k/n and syndrome depth. The gross code encodes one twelfth of its data qubits, and its depth-7 syndrome circuit costs seven two-qubit layers plus a measurement per round — the surface code's depth, on a graph the hardware does not have D[248]. The floor is the threshold, 0.8% under circuit-level depolarising noise D[248]; below it, suppression per distance step beats the surface code because the block carries more logical qubits per unit of syndrome information, not because any qubit is better.

Two structural penalties are real. Distance is not free: distance 12 in 288 qubits needs the long-range wraps, and deleting them collapses the family to something a heavy-hex lattice can host, rate advantage gone. Decoding is harder: the Tanner graph has short cycles, so minimum-weight matching does not apply and plain belief propagation does not converge; the practical choices are BP with ordered-statistics post-processing (accurate, too slow) or Relay-BP S[48]. The worst failure mode is anything the code does not see as Pauli — leakage, ion or atom loss — a sparse code having fewer redundant checks to localise a hyper-edge. Erasure conversion and leakage removal move this floor further than better gates.

Best demonstrated as of 3 Sep 2026: IonQ's eight codes on one 40-ion chain (June 2026, revised 14 Sep 2026) — break-even within error bars in one code the paper does not identify, 3.95 ± 0.68 s against 3.84 ± 0.48 s physical; the best bivariate bicycle lifetime in its Table II is [[24,4,4]]'s 3.39 ± 0.47 s, and [[18,4,3]], 4 logical qubits in 18 data ions, reaches 2.48 ± 0.40 s D[109]. Typical at scale: nothing — no BB code has run on more than 40 physical qubits (IonQ's [[30,4,5]], ancillas included), and none has hosted a logical two-qubit gate.

Dominant error term: on the ion run, post-selected leakage and loss; on the transmon run, two-qubit error over a depth-7 round on couplers up to 6.5 mm D[74], [109].

The code has no fab of its own, which is why it is a supply-chain question. On superconducting hardware it is unbuildable without multi-layer routing and long on-chip couplers: IBM's Loon, announced 2025-11-12 with six-way connections, longer c-couplers and low-loss routing layers, is the process vehicle, on 300 mm at Albany — no qubit count, coupler length or coupler fidelity published as of 3 Sep 2026 C[49]. Zhejiang's Kunlun processor shows the alternative: 84 air-bridged overlapping couplers, links to 6.5 mm, on a conventional process — good enough at 32 qubits, not at break-even D[74]. The single point of failure is a packaging and lithography capability held by two or three organisations: IBM/Albany, IQM's resonator hubs C[487], the Chinese academic fabs. The ion route has no fab constraint — connectivity comes from the motional bus, which is why IonQ got there first D[109]. Export-control exposure is indirect: the exposure sits in the hardware (US Export Administration Regulations ECCN 3A901; 3B904/3D901 for equipment and software), not the published mathematics.

Each round needs one mid-circuit measurement with reset per check qubit — 144 for the gross code — giving 144 syndrome bits per cycle per module, ~144 Mbit/s at a 1 µs cycle, an order of magnitude above a distance-7 surface patch for twelve times the logical qubits. The binding constraint is decode latency, not bandwidth: the decoder must return inside the cycle or the backlog grows without bound, and BP+OSD (belief propagation plus ordered-statistics decoding) cannot. IBM's FPGA Relay-BP shows it can be met in principle — 24 ns per iteration, under 1 µs mean per cycle — but it is a simulation-driven study, not a decode of live syndromes S[48]. At 10³ qubits the burden is unremarkable; at 10⁴ (≈35 modules, ~500 logical) the aggregate rate is ~5 Gbit/s and the decoder must be co-located, making NVQLink-class fabric (3.84 µs round trip) or a cold-stage ASIC a prerequisite P[324]. At 10⁶ nothing has been designed.

Architectures: primary code on three — trapped ions in a linear Paul trap with individual laser addressing (IonQ), trapped ions with electronic (laser-free, microwave-driven) gates and chip control (IonQ/Oxford Ionics) and colour-centre spin network nodes (Photonic Inc.); alternate on three — the transmon lattice with tunable couplers (IBM, IQM, Zhejiang), continuous-variable photonic GKP and silicon/germanium quantum-dot spins (Diraq). It requires millimetre-scale long-range on-chip couplers, ion shuttling, the ion-chain motional bus, or tweezer transport of atoms; it provides the syndrome stream Relay-BP-class decoders consume; it replaces the surface code; it conflicts with nearest-neighbour-only connectivity — heavy-hex is insufficient without c-couplers. Price of switching: ≈10× in qubits gained; planarity, matching decoders and the body of lattice-surgery technique lost, the BB replacement (adapters, logical processing units) existing only on paper S[496]. It is one of the few code-layer nodes reaching superconducting, ion and photonic carriers at once, its value set by whichever delivers degree-6 connectivity first. Derived clock: it sets d₂ — seven gate layers — so the round on trapped ions with electronic gates is 1.52 ms, gate-set, against a measured ≈1–5 ms; the transmon lattice's round is 0.65 µs derived against the 1.1 µs QEC cycle D[1]. Neighbouring empty slot: a hardware logical CNOT between two BB blocks.

Break-even here is a memory comparison: logical lifetime against the best physical qubit on the same device, over repeated syndrome rounds and a destructive final readout. IonQ's 3.95 ± 0.68 s versus 3.84 ± 0.48 s (the physical baseline, 3·T2: 3.3 ± 0.9 s in the June version, revised in the arXiv version of 14 Sep 2026) overlaps within one standard deviation, and is stated with leakage post-selection D[109] — defensible for a memory claim, but it removes exactly the error class a sparse code handles worst, and the acceptance rate is not in the abstract. The protocol also misses what a code is for: no BB demonstration anywhere reports a logical two-qubit gate, so the overhead advantage is verified only for storage. Value conflict: the main report lists a Harvard/QuEra [[16,6,4]] run beside IonQ's; that is a high-rate block code, not a bivariate bicycle code, and no primary source was found — treat IonQ and Zhejiang as the only BB hardware results. IBM's July-2026 "70 logical qubits, 468 T gates" is an error-detecting* spacetime code and does not belong here D[46].

IonQ's 3.95 ± 0.68 s break-even lifetime follows the introduction of its arXiv version of 14 Sep 2026; that version's Table II lists no code at 3.95 s, and its best lifetime there is BB[[24,4,4]] at 3.39 ± 0.47 s. Not published: the code, round count and per-round logical error behind the 3.95 s figure, and a dated qLDPC patent-family count. Photonic Inc.'s "up to 20× fewer physical qubits" is a company claim with no stated logical error rate. IBM's blog "10× fewer qubits" rounds the Nature comparison of 288 against ≈3,000 physical qubits, a ratio that depends on the assumed physical error rate.

Money.

• 2025-11-06 · DARPA · QBI Stage B, eleven teams · up to $15 M each (USD) · announced G[65]fact
• 2026-05-12 · Photonic Inc. · final close · $200 M at $2 B (USD) · Microsoft among returning investors · $350 M total · closed P[186]fact
• 2026-05-21 · IBM/Anderon · CHIPS letter of intent · $1 B + $1 B IBM cash (USD) · Dept of Commerce · LOI G[300]fact
• 2026-06-02 · IBM · five-year quantum commitment · >$10 B (USD) · announced C[57]fact
• 2026-07-31 · IonQ · SkyWater, captive ion-trap fab · ~$1.8 B (USD) · closed C[19]fact

Market & supply chain. Nobody sells qLDPC. What sells is the connectivity that makes it usable — multi-layer superconducting interconnect (IBM at Albany, IQM's resonator hubs), ion-trap chips (IonQ owns SkyWater C[19]) — and the decoding that makes it affordable (IBM in-house, NVIDIA's fabric P[324]). Concentration risk is extreme: one organisation holds both the code and the only connectivity vehicle built for it. Unit economics are the case, ~24 physical per logical against ~1,000 for a distance-25 surface patch D[1], [248]. Only G3 and G4 pay for it.

IP & standards. No bivariate bicycle patent family appears in the Justia index under that phrase as of 2026-09-03 — IBM published rather than fenced P[672]. Enforceable IP sits one layer down: IBM US 12,517,856 (granted 2026-01-06) and US 12,587,192 on resonator chains with tunable inductive couplers (granted 2026-03-24) G[498]fact. Decoder IP is filed by others: KAIST US 12,346,774 (2025-07-01), Princeton US 11,941,489 (2024-03-26), US 2026/0172053 on qLDPC decoders (2026-06-18) G[672]. Stim, PyMatching and BP+OSD carry the field; no standard exists.

Roadmaps & track record. IBM: Kookaburra, qLDPC memory plus logical processing unit (promised 2025-06-10 · for 2026 · not delivered as of 2026-09-03); Cockatoo modules (2025-06-10 · 2027 · pending); Starling, 200 logical and 10^8 gates (2025-06-10 · 2029 · pending) R[72], [481]. The 2022-05-10 roadmap had promised Kookaburra as a 1,386-qubit processor for 2025 C[313]fact; IBM has shipped every published component of the stack except the code itself, so 2026 is optimistic and 2027 plausible. IQM: qLDPC demonstrators (2026-01-05 · 2027-28 · pending) C[487]. Photonic Inc.: SHYPS announced 2025-02-11, peer-reviewed 2026-08, still no hardware C[670]P[671].

Strategic reading. If BB codes work at scale, IBM wins the architecture argument it has made since 2024 and every surface-code roadmap absorbs a 10× overhead disadvantage or switches. Ions and photonic-linked platforms win incidentally; the loser is any platform whose only lever is planar lithography. Bargaining power sits with whoever controls high-degree interconnect, not the code's authors.

Confirm within 12–24 months if IBM demonstrates a gross-code memory below break-even with real-time decoding (Kookaburra, promised 2026), if any group performs a logical two-qubit gate between BB blocks, or if a BB result appears without leakage post-selection. Demote if Kookaburra slips past end-2027, or if Loon's c-coupler fidelity when published is poor enough to eat the 10× rate advantage. Best case by 2029: Starling-class machines, 200 logical qubits at ≈24–40 physical each, factoring estimates falling to the 10⁵-qubit range S[7], [29]. Worst case: a 20-qubit laboratory curiosity, connectivity costing more fidelity than the rate saves.

Open questions: (1) what two-qubit fidelity does a millimetre-scale coupler cost, and does it exceed the rate advantage? (2) can Relay-BP hold its latency on live syndromes? (3) do BB logical gates via adapters beat lattice surgery once the logical processing unit is counted? (4) how does the threshold move under leakage and loss rather than depolarising noise? (5) does anyone outside IBM adopt this family? Watch the Loon fidelity disclosure and IQM's 2027 demonstrator.