IQM Emerald (IQM Crystal 54)

Raveh Neeman

doi:10.5281/zenodo.22674814

IQM Quantum Computers · superconducting circuits · DEPLOYED (21 Jul 2025 (LRZ 11 Feb 2026)) · 54 physical qubits · access: cloud (Amazon Braket, IQM Resonance) + on-prem sold

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: tunable transmon

gate mechanism: tunable couplers, native CZ

connectivity: Crystal square lattice, degree 4

control: room-temperature RF; modular decoder architecture with NVIDIA NVQLink

control placement: room-temp

readout: multiplexed dispersive, 240 ns pulse at 99.94% on a test chip

gate evidence: a published figure (source class not yet tagged)

codes: hagiwara_nakayama_deletion, quantum_repetition

flags: test chip, not a system

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▣ Fig. 1a (quasi-lumped circuit: two transmons + floating coupler) ✅ tunable transmon; 54 qubits, Amazon Braket GA 21 Jul 2025; median 1Q 99.93%
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 bare transmon two-level subspace; no encoding beyond the physical qubit
3 Gate mechanism	Tunable-coupler CZ / iSWAP · primary ▣ Fig. 1a (floating coupler qubit); Fig. 3 (interleaved RB of CZ over 40 h) ✅ tunable couplers, native CZ; median 2Q 99.5% at 54 q (Jul 2025); 2-qubit test chip CZ 99.93% over 40 h (Aug 2025), not a system median
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▥ ✅ Crystal square lattice, degree 4
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▣ Appendix A Fig. S1 (experimental setup schematic) ✅ room-temperature RF; IQM real-time QEC demonstrator 20 q + Zurich Instruments ZQCS + NVIDIA NVQLink, <4 µs end-to-end (Mar 2026)
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ▣ Fig. 4f-i (single-shot readout clouds); Table S1 (resonators/Purcell) ✅ multiplexed dispersive, 240 ns pulse, >99.94% on a 2-qubit test chip (Aug 2025), not a system median
7 Code	Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) · primary ▦ tutorial output ✅ bit-flip repetition code, 4 data qubits, 2 syndrome rounds, hardware output in the vendor documentation (sweep 7 Oct 2026, source read) Non-local qLDPC codes (bivariate bicycle, 'gross') · alternate ▤ ✅ not run: directional tile / barbell qLDPC codes with NN iSWAP on a planar grid, ≈30 circuit qubits per logical, exemplar [[323,14,15]] (theory, Jun 2026)
8 Decoder	GPU decoding via NVQLink · alternate ▨ ✅ not deployed: GPU decoding over NVIDIA NVQLink with Zurich Instruments ZQCS; 20-q demonstrator <4 µs end-to-end loop (Mar 2026) — none — nothing in this layer ▨ 🔎 no decoder deployed on Emerald; targets dec_gpu over NVQLink; real-time QEC demonstrator only
9 Interconnect	— none — nothing in this layer ◌ 🔎 monolithic single 54-qubit module, no interconnect
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ◌ 🔎 superconducting-qubit fab (IQM); no machine-specific fab source

Standard records

2Q error under full-width parallel operation → 7.00e-4 · best (99.93% CZ over 40 h on a 2-qubit test chip)

test chip, not a system median · Aug 2025 · source

2Q error under full-width parallel operation → 5.00e-3 · typical (median 2Q at 54 q, 99.5%)

not on the cited roadmap page · Jul 2025 · source

SPAM error → 6.00e-4 · best published superconducting readout (>99.94% in 240 ns)

Aug 2025 · source

feed-forward latency → 4.0 µs · best for a European superconducting vendor (end-to-end real-time QEC loop, 20 q)

Mar 2026 · source

evidence: ✅ 8 / 12