GPU decoding via NVQLink dec_gpu

A low-latency RDMA-over-Converged-Ethernet (RoCE) path between a QPU's control electronics and a GPU, with an open-source FPGA core on the quantum side, so decoding and in-loop calibration run as CUDA software rather than a bitstream. NVIDIA announced it on 2025-10-28, naming 17 quantum-computer builders, five control-electronics vendors and nine US national laboratories C[531]; the numbers followed on 2025-11-17 C[324]. Attributes: d = platform-agnostic, reaching superconducting, trapped-ion QCCD and neutral-atom architectures; e/f/g = no control modality, corrects Pauli syndrome errors, no fabrication — commodity GPU and Ethernet hardware (graph record).

Two budgets make up the round trip, and they must not be read the same way. Transport is bounded: 3.84 µs mean, 0.035 µs standard deviation, 3.96 µs maximum over 1,000 samples C[324] — the tightness matters more than the mean, because a feedback loop is sized by its tail. Decode is not: BP+OSD (belief propagation plus ordered-statistics decoding) on a GH200 against Quantinuum's Helios gives a 67 µs median for Bring's code, taking an 8-logical-qubit memory from 4.95 ± 0.67% to 0.925 ± 0.38% error, a 5.4× gain C[324]. Their sum, ~71 µs, is therefore a typical round trip, not a bound: only the transport term has a published maximum.

Whether 67 µs is slow depends on which clock it must meet. For memory the requirement is throughput, not per-cycle latency: Google sustained 10⁶ cycles at d=5 on a 1.1 µs cycle with a real-time decoder of 63 µs mean latency D[1] — the same order as the GPU figure — because a sliding window pipelines cycles instead of decoding each within one. Reaction time is the hard constraint, and it binds only where an operation is conditioned on a decode: magic-state injection, feed-forward, lattice surgery. That distinction, not the raw microseconds, decides where this layer is usable. GPU decoding is therefore comfortable on millisecond-cycle ion and atom platforms, adequate for superconducting memory, and unproven on the reaction-limited path. What moves the floor: kernels exploiting GPU parallelism rather than ports of serial algorithms.

GPU decode time dominates at ~17× the network hop, so the interconnect is not what has to shrink. No published result runs GPU BP+OSD and an FPGA decoder on identical traces.

No fabrication process. The GPU side is NVIDIA silicon — GH200 for Helios, RTX PRO 6000 Blackwell Max-Q for the networking demonstration C[324] — with no AMD or Intel equivalent as of 2026-09-04. The network side is deliberately unlocked: RoCE is a standard and NVIDIA published an open-source FPGA core for the QPU endpoint C[324], which let five control-electronics vendors integrate it C[531]. The asymmetry is the commercial design — give away the interface, sell the accelerator. Nothing is priced; it ships as a reference architecture with a sign-up page C[531]. Export exposure is inherited from US controls on advanced GPUs, not from a quantum ECCN.

The loop is control electronics → RoCE → GPU → back, at 3.84 µs plus decode. Helios is 98 physical qubits D[105], so nothing at 10³ has run end-to-end. At 10⁴–10⁶ the question is whether decode time grows with code size faster than throughput grows per GPU generation, and whether batching across logical blocks keeps the budget flat; no source states either. The offsetting argument, unquantified: one GPU cluster can serve several QPUs, which an FPGA bolted to one rack cannot.

It requires nothing upstream and replaces FPGA-based real-time decoding, trading a fixed bitstream for software changeable between shots; the graph records it as the primary decoder on trapped-ion QCCD and as an alternate on the transmon lattice with tunable couplers and the alkali Rydberg tweezer array — one decoder across three families. Derived clock contribution: ~71 µs per decode round trip — transport plus median decode (2 s.f.) — 1–7% of a 1–5 ms ion or atom cycle but ~65 cycles of a 1.1 µs superconducting one D[1]. Switching cost is a rack and a software stack, not a code change — the opposite of the qLDPC decoders. Adjacent empty slot: an independent cross-vendor benchmark.

Both headline numbers come from NVIDIA's own blog, co-developed with Quantinuum, and are not peer-reviewed C[324]. The 5.4× carries uncertainties — better practice than most vendor claims — but it is one code on one machine, and the IQM demonstrator is trade press P[239]. No comparison exists against Relay-BP D[48] or Riverlane's decoder D[238] on the same syndromes, so "GPUs are slower than FPGAs" compares numbers from different codes and machines.

Not published: how GPU decoding time scales with code size or logical-block count at 10⁴–10⁶ qubits, and NVentures' separate investments in Quantinuum, QuEra and Alice & Bob, of which only the round totals are public. The launch release's headline counts of 17 builders and nine labs do not tally exactly with the names it lists.

Who.
| Organisation | Role | Country | What exactly they do with this technology | Evidence |
|---|---|---|---|---|
| NVIDIA | Developer | USA | Built NVQLink and the nv-qldpc-decoder; supplies the GPUs | C[324], [531] |
| Quantinuum | User | USA/UK | Only published deployment: Helios plus GH200 running BP+OSD | C[324]fact |
| IQM | User | Finland | Real-time QEC demonstrator over NVQLink under 4 µs end-to-end | P[239]fact |
| Zurich Instruments | Supplier | Switzerland | Control electronics carrying the NVQLink endpoint | C[531] |
| DARPA | Funder | USA | QBI Stage B funds several of the named QPU builders | G[65]fact |

Money. 2025-10-28 · NVIDIA · launch, 17 builders / 5 control vendors / 9 labs · no financing disclosed · announced C[531]. 2025-09-04 · Quantinuum · $600 M at $10 B pre-money, NVentures participating · closed Cfact. 2026-05-22 · Alice & Bob · Series B extension with NVentures · closed Cfact. 2026-07-26 quarter · NVIDIA · revenue $96.2 B, Data Center $89.0 B, +106% y/y, quantum unmentioned · reported G[737] — the economics of this layer in one line.

Market & supply chain. No market yet — no price, SKU or licence terms disclosed C[531]. The chain splits: open interface, single-sourced accelerator, so concentration risk is the decoder host, not the link. Goal exposure is broader than any FPGA decoder — G3/G4 as a decoder, G2 because the same path serves mitigation and calibration, G7 because national-lab deployments are procurement-shaped.

IP & standards. No patent family specific to NVQLink was found in any named database. The standards posture is the interesting part: RoCE is an existing Ethernet standard and the QPU-side core is open source C[324], so NVIDIA standardises the boundary it does not sell. Third parties build against CUDA-Q QEC Pfact.

Roadmaps & track record. NVIDIA: (2025-10 · launch with 17 builders · delivered, one published deployment three weeks later) C[324], [531]; (2025-11 · partners to deploy on future processors · only Helios confirmed) C[324]. IQM: (2026-03 · demonstrator · delivered) P[239]. Launch-to-first-deployment was effectively zero; the gap between 17 announced builders and one published deployment is the number to watch.

Strategic reading. If GPU decoding wins, every fault-tolerant machine becomes a recurring GPU customer and decoding stops differentiating QPU vendors — good for builders without FPGA engineering, bad for Riverlane and IBM's in-house route. NVIDIA loses little if it fails: quantum does not appear in a $96.2 B quarter G[737], so this is a cheap option on the classical half of a future stack. The substitution threat is a decoder ASIC nobody sells. Bargaining power sits with NVIDIA on the accelerator and the control vendors on the endpoint.

Falsifiable (12–24 months): confirm if a second QPU vendor publishes an NVQLink decode loop with numbers by end-2027; demote if published deployments still number one. Best case 2029: GPU decoding is the default on ion, atom and superconducting memory, reaction-limited operations handed to a small local FPGA. Worst case: 17 builders yield two deployments and dedicated hardware keeps the loop. Open questions: how decode time scales with code size and block count; whether anyone reports tail rather than median latency; whether AMD or Intel field a rival host. Watch: a second deployment and any independent benchmark.