Trapped ions — QCCD (transport between zones) on the map bar: QCCD ions

The architecture in the report (§8.3)

8.3.4 QCCD ions — Trapped ions — QCCD (transport between zones) (ion_qccd)

The idea. The quantum charge-coupled device (QCCD) keeps every gate in a small, cold crystal and moves the ions instead: electrode voltages carry hyperfine clock qubits through junctions or grid sites (cx_qccd) into zones where a Mølmer–Sørensen laser gate acts on two ions [D][97]. The qubit survives the ride; the motion does not, so every move costs splitting, merging and re-cooling. The bet: trade clock for fidelity and connectivity (any pair meets, at an error no static layout matches), then cut transport time faster than rivals close the fidelity gap. On Helios a two-qubit gate takes ~70 µs, a full-width layer ~55 ms [D][97].

What it needs. Ion shuttling requires junction or grid traps, whose electrodes grow with the register: 1,228 on Helios, driven by 273 voltages [D][97]. High-rate concatenated codes require the all-to-all that transport buys; on Helix, moving an ion relabels a qubit, so automorphism gates are free [P][5]. Carrier, encoding, connectivity, readout and interconnect hold one technology each; at gate, control and fabrication the laser and electronic branches are replaces pairs, so transport alone defines the architecture. The colour-code alternate conflicts with matching. The derived syndrome round: 9.66 ms, 9.04 ms of it transport [S] (§7.4).

Where it stands. Seven machines, four counted as devices: Quantinuum's H1-1, H2-1 and Helios and Universal Quantum's iQPU (Helix, a code on Helios, is a component); Sol (2027, 192 qubits) and Apollo are plans [R][118]. Helios, the largest, holds the best median two-qubit error, 7.9×10⁻⁴ across all pairs, with SPAM 3.3×10⁻⁴ [D][97]; on it ran 48 error-corrected logical qubits at ~1×10⁻⁴ logical gate error [D][105] and a Helix memory at 4.6×10⁻⁵ per logical qubit per cycle, not post-selected [P][5]. The iQPU publishes no gate error; no built machine has an interconnect technology.

Exceptions and borrowings. Integrated photonic delivery, the architecture's stated direction, is in no built machine: Helios drives each operation with focused free-space beams parallel to the chip surface [D][97] — so the free-space technology is the architecture's primary since 26 September 2026 and integrated photonics its alternate; the H1-1 and H2-1 cells are press-level. Quantinuum's decoders fall outside layer 8: real-time lookup tables on H1-1 and H2-1 (∅G-lut), Helix's offline block decoder (∅G-frontier). Helix is a code on Helios, not a second trap, and is counted as a component. The iQPU is a hybrid: microwave gate, chip control and foundry fabrication from the electronic-control architecture, transport from this one; it fits both with seven technologies each. Its interconnect is the gap ∅G-ionmatter: ions carried between two chip modules at 2,424 transfers s⁻¹, transport infidelity below 7×10⁻⁸ [D][117], the architecture's one demonstrated module link, credited in the family's scaling score (§2.3), absent from the map. Transport crosses the module edge; layer 9, photonic only, is drawn too narrowly. The iQPU's fabrication cell reads trap microfabrication on a commercial 200 mm line, the CMOS-foundry technology a press-level alternate. Innsbruck and QUARTET borrow ion shuttling as an alternate.

The next test. Sol decides it (§5.2): confirm if it ships in 2027 with ≥99.9% two-qubit gates on the 2D grid and a full-width layer below 10 ms, 5× faster than Helios; demote if it slips past 2027 or its layer stays within 2× of 55 ms: a code demonstrator, not an algorithm runner. The builder's own bar is lower — Quantinuum promised Sol "about twice as fast as Helios" — and meeting it would confirm the promise, not the architecture's claim to run algorithms, which needs the 5×. Second signal: a third transport-linked module.

What the builders say. Quantinuum's case for transport is connectivity: moving ions lets any qubit entangle with any other, enabling, it says, codes that fixed layouts cannot run [C][834]; its Helix code concatenates codes in a way it calls extremely difficult without mobile qubits [C][835]. In 2024 it promised Sol with hundreds of physical qubits below 2×10⁻⁴ two-qubit error, about twice as fast as Helios, and Apollo with hundreds of logical qubits at logical error below 10⁻⁶ [R][836]; since June 2025 Apollo is dated 2029 [R][837]. In August 2026 Sol's trap chip was back from fabrication for a 2027 launch, and Apollo was on schedule for 2029 [R][123], [124]. Universal Quantum links trap chips by carrying ions between them, a route it says scales to millions of qubits [C][838].

Machines of this architecture (register: 7, of them 4 devices, 4 gate-capable). Quantinuum — Helios (deployed, 98), System Model H2 (H2-1, H2-2) (deployed, 56), Helix architecture on Helios (demonstrated, 20), System Model H1 (H1-1) (deployed, 20), Apollo (planned), Sol (planned); Universal Quantum — iQPU / UQConnect (demonstrated, 64).

Cells outside the architecture's slots (4). System Model H1 (H1-1): L8 ∅G-lut (Atlas gap — real-time lookup-table decoding of Steane [[7,1,3]] in-loop since 2021; no LUT node among ); System Model H2 (H2-1, H2-2): L8 ∅G-lut (Atlas gap — real-time lookup-table decoder); Helix architecture on Helios: L8 ∅G-frontier (Atlas gap — Frontier: block-specific offline decoder for concatenated high-rate codes, neither matchin); iQPU / UQConnect: L9 ∅G-ionmatter (Atlas gap — chip-to-chip matter link: UQConnect physically transfers ions between trap modules, 2,424 ).