Trapped atomic ion ion

A trapped-ion qubit is a single atomic ion — ytterbium, barium, calcium or strontium — confined by rf and static fields above microfabricated electrodes, with logic in hyperfine, Zeeman or optical levels. Ions in a chain repel, so they share quantised motional modes; a spin-dependent force on those modes turns motion into a bus that entangles any pair. Cirac and Zoller proposed it in 1995; Wineland's NIST group demonstrated the first gate the same year, between one ion's internal state and its motion, and two-ion gates followed in 1998–2003. Everything commercial today is that idea plus surface-electrode microfabrication.

Attributes (technology graph): carrier affinity 0.0 — wholly natural, every ion identical by physical law, no fabrication variance to calibrate out; entangling time ≈ 63 µs (10^−4.2 s), deterministic, no heralding; readout by fluorescence on a cycling transition, ≈ 10 µs, non-destructive, mid-circuit capable; mobility by physical transport — ions are shuttled, not wired; control optical, at room temperature; error structure as the code sees it coherent, leakage, Pauli; manufacturing MEMS-class surface-electrode traps.

Trap frequencies of a few MHz set the clock. Spin–motion coupling scales with the Lamb–Dicke parameter times the drive, so a gate much faster than a motional period either excites the wrong modes or needs optical power that reintroduces scattering; µs-to-hundreds-of-µs gates are a physical compromise, not an engineering lapse. Memory is the opposite: in magnetically insensitive clock states one ion holds coherence beyond an hour D[104], five to six orders longer than a superconducting qubit. Idle error is nearly free; idle time is what costs.

The floor belongs to the drive, not the carrier: laser gates carry an irreducible spontaneous-emission floor, and 8.4(7)×10⁻⁵ two-qubit error at Doppler temperature without ground-state cooling D[102] shows it is removable. What remains is anomalous heating from electrode surfaces, mode crowding as chains lengthen, and background-gas collisions that reorder or eject a chain. That last is the architectural problem: a decoder built for stochastic Pauli noise instead sees ions leak into metastable manifolds or vanish. Leakage is small enough to quote — 1.1×10⁻⁵ per Clifford on Helios D[97] — but quoted separately because it is not Pauli. Cryogenic traps, sympathetic cooling, metastable erasure encodings and better vacuum would move the floor.

Best-demonstrated and typical-at-scale have converged unusually far: Helios runs 98 Ba⁺ qubits at 7.9×10⁻⁴ two-qubit error with all-to-all connectivity, within an order of magnitude of the record. The gap is speed — the gate is ≈ 70 µs, but a full-width layer takes ≈ 55 ms once sorting, transport and re-cooling are counted; transport was ~60% of runtime on H2 D[97], [110].

The dominant error term at scale is not the gate: it is the cost of moving ions — transport excitation, re-cooling, re-ordering — plus leakage the decoder cannot absorb. High-rate code demonstrations discard 75–97% of shots at depth D[105].

Traps are MEMS-class silicon parts, not qubit-defining lithography: the ion is perfect, so wafer variance shows up as electrode geometry and surface quality, never as qubit-to-qubit spread. Two fabs matter. Infineon runs a dedicated QPU platform in Villach on 6- to 12-inch wafers with anodic wafer bonding; its Generation-3 traps add out-of-plane electrodes claimed to raise confinement ~10×, with eleQtron (three generations), Oxford Ionics, Innsbruck and ETH Zürich as named users C[320]. Honeywell fabricates Quantinuum's traps in-house — Helios carries 1,228 electrodes D[97] — and the Sol grid trap is back from fabrication and in validation C[123]; Infineon separately partnered with Quantinuum on next-generation traps in 2024-11 C[321]. Infineon is a single point of failure for IonQ/Oxford Ionics, eleQtron and Universal Quantum at once P[322] — which is what IonQ's ≈ $1.8 B purchase of SkyWater (closed 2026-07-31) buys its way out of C[19].

The second concentration is optical: TOPTICA (> €140 M revenue, ~600 staff) supplies most major ion experiments, and the UV end — 369 nm for Yb⁺ — is the constrained part P[322]. Vacuum hardware and atomic sources are commodity; photonic interconnects re-import a cryogenic dependency through SNSPDs P[322]fact. Unit economics: AQT delivered a 20-qubit rack to LRZ / Munich Quantum Valley for ≈ €9.8 M (2023-12-05, Bavarian Hightech Agenda) C[323] — ≈ €0.5 M per qubit, turnkey. Export exposure runs through the September-2024 US quantum ECCNs; a bare trap chip's classification is unverified here.

Per-ion optical addressing is what fails to scale linearly: Helios needs at least seven laser wavelengths alongside 1,228 electrode drives D[97]. Readout is cheap — fluorescence onto a PMT or camera in ≈ 10 µs, non-destructive and natively mid-circuit. Latency demands are mild: IonQ assumes 1–5 ms syndrome cycles D[111], inside NVQLink-class round trips C[324]fact.

The wall moves with N. At 10³ it is drive-source count and optical-table area; the WISE study argues a fully connected 1,000-ion machine could run from ~200 sources with in-trap switching electronics, at 40–2,600 gate layers per second S[325]fact — paper design, no chip built. At 10⁴ it is inter-module: remote entanglement stands at 9.7 s⁻¹ over 2 m (Bell 96.9%) D[115] and 250 s⁻¹ in a lab D[116] against ~10⁴ s⁻¹ needed. At 10⁶ it is yield and laser power. Gate generation and microwave control belong to the sibling briefs.

The carrier feeds three architectures, as the primary carrier of each: Trapped ions — QCCD (transport between zones) (Quantinuum, Universal Quantum), Trapped ions — linear Paul trap with individual laser addressing (IonQ's Aria, Forte and Tempo; AQT; Qudoor; Quantum Art) and Trapped ions — electronic qubit control (laser-free, microwave-driven gates) (IonQ/Oxford Ionics, eleQtron, QUDORA). It requires surface-electrode trap microfabrication and optical/mechanical assembly, and is the substrate for the Mølmer–Sørensen gate, the electronic near-field microwave gate, metastable "omg" erasure encoding, shuttling, fluorescence detection and the ion–photon link. It replaces and conflicts with nothing: ions are a self-contained column, which is why switching away is total — nothing above the carrier survives but the compiler.

Derived clock = sum of the syndrome round: gate layers + transport + readout + reset. On the QCCD architecture transport dominates: ≈ 9.7×10⁻³ s per round, 9.0 ms of it transport, against a ≈ 5.5×10⁻² s full-width layer D[97], [110]. On the electronic-gate architecture the round is ≈ 1.5×10⁻³ s, set by the gate layers D[102]. That six-fold gap is the platform's defining number. Neighbouring empty slot: a cryogenic chip-integrated drive layer for ion traps — the SFQ/cryo-CMOS analogue — has no product-scale occupant.

Headline two-qubit numbers come from randomised-benchmarking variants. The 8.4(7)×10⁻⁵ record is a subspace-leakage RB on one ion pair at Doppler temperature, not a device-wide figure, and the retrievable text gives no gate duration D[102]. Helios's 7.9×10⁻⁴ is an averaged device figure, consistent with the earnings language "99.921%" C[123]. Quantum volume and #AQ are vendor-defined composites with no replication protocol C[98], [99]. RB also runs statically, so shuttling and re-cooling are invisible to quoted gate errors. Logical results carry an acceptance fraction (0.62(2) D[105]) and IonQ's break-even is leakage-post-selected D[109]; neither is unconditional. No ion platform has published Λ-type distance scaling.

Conflicts. The electronic gate's duration is 225.8 µs (2025) or ≈ 120 µs (2024) in the technology graph and unstated in the 2025 abstract — unverified. Quantinuum's "near five-nines logical fidelity with a novel QEC code family" C[123] outruns the published 1.0–1.2×10⁻⁴ logical gate infidelity D[105]; the code family is unpublished, so the D value stands. IonQ's Tempo is marketed at "99.9%" and #AQ 64 with no published gate times C[99], [326].

The main report gives IonQ Forte's Mølmer–Sørensen gate times on 30+-ion chains (550–883 µs, median 672 µs; single-qubit 110 µs) without a numbered source. Not published: the export-control classification of a bare, un-populated ion-trap chip under the September-2024 US quantum ECCNs (4A906 family) and allied national controls; any funding amount, date, valuation or qubit count for Qudoor (AbaQ, 32+ claimed patents), the only Chinese ion-trap vendor named in 2026 sources; any delivery, milestone or fidelity result against Universal Quantum's €67 M DLR contract as of 2026-09-03; an equity round with a stated amount and date for AQT or QUDORA Technologies (Braunschweig; Tokyo subsidiary opened 2026-05); and Quantinuum's bookings, backlog, Helios unit sales or customer names, absent from its Q2-2026 release.

Money.

• 2022-11-02 · Universal Quantum · DLR contract · €67 M · announced P[328]fact
• 2023-12-05 · AQT · contract, 20-qubit system for LRZ · ≈ €9.8 M · Bavarian StMWK/StMWi · closed C[323]
• 2025-11-06 · IonQ, Quantinuum · DARPA QBI Stage B · up to $15 M each · selected G[65]fact
• 2025-10-12 · IonQ · equity · $1.0 B + $2.0 B at $93/share · closed fact
• 2025-09-04 · Quantinuum · round · $600 M at $10 B pre-money · NVentures, Quanta, QED, JPMorgan · closed G[122]fact
• 2025-09-17 · IonQ · M&A Oxford Ionics · $1.075 B · closed C[18]fact
• 2026-04-27 · Quantum Art · Series A extension · $100 M → $140 M · closed P[125]fact
• 2026-05-05 · eleQtron · Series A · €57 M · backlog €54 M · closed C[128]fact
• 2026-06-03 · Quantinuum · IPO, Nasdaq QNT · $1.68 B gross at $60/share · closed G[123]fact
• 2026-07-31 · IonQ · M&A SkyWater · ≈ $1.8 B · closed C[19]fact
• 2026-06-30 · Q2 FY26 revenue · Quantinuum $8.0 M, cash $2.1 B, guidance $28–32 M; IonQ $80.1 M, cash $3.0 B, guidance $280–290 M C[123], [326]

Market & supply chain. Equipment money sits with TOPTICA, Infineon and commodity vacuum vendors; concentration risk is real in two places only — UV lasers and Infineon's fab, which underpins three otherwise-independent developers P[322]. Against ≈ €9.8 M for a 20-qubit rack C[323], sector ion revenue is about one large system per quarter plus cloud access. Goals that pay: G1 (Tsinghua's simulator), G2 and G5 (cloud), G3 (Helios logical qubits, IonQ's qLDPC memory), G7 (AQT racks, eleQtron's backlog), G6 in prototype. G4 is funded by capital markets and DARPA, not customers.

IP & standards. Named families: Oxford Ionics' electronic qubit control and the WISE in-trap switching architecture S[325]; Honeywell/Quantinuum QCCD junction and grid-trap patents behind 2.5 kHz ion exchange and 4 m/s transport D[113]; Infineon's anodic-bonding 3D-electrode process C[320]; ID Quantique's detector portfolio, now IonQ's C[19]. No dated ion-specific patent count from a named database was found; PatSnap's landscape published on 2026-06-30 counts 546 quantum patent families for IonQ, eighth among assignees, but breaks out no trapped-ion line Pfact. No ion-specific standard exists.

Roadmaps & track record. Quantinuum: Helios (promised 2024-09-10 · for 2025 · launched 2025-11-05) fact; Sol (promised 2024-09-10 · for 2027 · trap chip fabricated, in validation); Apollo (for 2029 · "on schedule", prototypes only) C[123]. Credibility high — promised dates met — except the unpublished five-nines code family. IonQ: 4,000 qubits (promised 2020 · for 2026 · missed ~40×) P[132]; 256 qubits at 99.99% (promised 2025-06-13 · for 2026 · slipped to H1 2027) R[132]; 10,000 on one chip (for 2027 · no published 2D-trap heating or interconnect data). Credibility mixed: the physics is peer-reviewable, the schedules are not. AQT delivers its QV records on time; Universal Quantum has announced nothing against its 2022 contract P[328].

Strategic reading. If ions win, Honeywell and Infineon capture structural rent — one through vertical integration nobody can copy, the other as the only merchant trap fab — and TOPTICA becomes the choke point. IonQ's SkyWater purchase converts a supplier dependency into an owned asset: a bet that trap fabrication, not qubit physics, is the scarce input. The substitution threat is not superconducting circuits (faster clock, worse fidelity) but neutral atoms: same natural carrier, same optics-heavy engineering, thousands of sites already, fidelity closing. Bargaining power still sits with the platform vendors: Infineon's quantum unit is a rounding error inside a €15 B company P[322] and cannot price like a monopolist.

Confirm if: Sol ships in 2027 with ≥ 192 physical qubits on a 2D grid trap and a published layer time better than ≈ 55 ms; any ion vendor publishes Λ > 1 scaling across d=3→5→7; remote entanglement passes 10³ s⁻¹. Demote if: IonQ has not shown 256 qubits at 99.99% by end-2027 (already slipped once); Sol leaves layer time unimproved; or the five-nines code family stays unpublished a year on.

Best case by 2029: Apollo lands with hundreds of logical qubits at 10⁻⁶–10⁻¹⁰ and ions own early fault tolerance, the clock deficit absorbed by depth-hungry algorithms. Worst case: 2D scaling multiplies transport cost instead of amortising it, layer time stays in tens of milliseconds, and ions become the high-fidelity low-throughput instrument for QEC research while neutral atoms and superconducting circuits take the volume.

Open questions: does grid-trap heating scale with zone count or electrode area? Can leakage be turned into erasure fast enough that decoders stop paying for it? What is the electronic gate's real duration at full width? Is 10⁴ s⁻¹ remote entanglement reachable at all? Who second-sources Infineon?