QUARTET
QUARTET
architecture: Trapped ions — electronic qubit control (laser-free, microwave-driven gates) · Open on the map
Register profile — the machine's variant of its architecture
qubit type: hyperfine qubit
gate mechanism: Electronic Qubit Control: chip-integrated electronics generate the gate fields, no gate lasers
connectivity: single chain (2-D connectivity promised via Q-Surge, no timeline)
control: chip-integrated microwave control; the 1.5e-7 1Q gate error without magnetic shielding is not on the cited page
control placement: on-chip microwave
readout: fluorescence
gate evidence: no published figure
flags: count from secondary source, hero-pair number
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Trapped atomic ion · primary ▣ Fig. 1 (chip with 2D grid of unit cells, ions near local tuning electrodes); §III Experiments (40Ca+ ions 40 um above a seven-zone trap at ~5 K) ✅ trapped-ion hyperfine qubit; QUARTET qubit count not published (32-qubit processor generation per secondary source); installed NQCC Harwell 13 Aug 2025 |
| 2 Encoding | Hyperfine / clock-state qubit · primary ▤ §III Experiments (qubit in 4S1/2 Zeeman sublevels of 40Ca+, 240 MHz at 8.5 mT) ✅ ground-state hyperfine qubit; family-determined, species not stated in sources |
| 3 Gate mechanism | Electronic microwave gate (ions, laser-free: near-field or static gradient) · primary ▣ Fig. 3 (two-qubit MS interactions via currents through the shared trace, B-field gradient); §III.2 High-fidelity tunable two-qubit gates; App. B ✅ Electronic Qubit Control: chip-integrated electronics generate gate fields, no gate lasers; 2Q fidelity 99.99 % (21 Oct 2025), up from 99.97 % (2024) |
| 4 Connectivity / transport | Ion-chain motional bus (all-to-all in chain) · primary ▤ §III Experiments (seven-zone single-layer linear trap, up to 10 qubits; probe ions shuttled to the central zone) ✅ single chain today (degree 31 for the 32-qubit generation); 2-D connectivity promised via Q-Surge, no timeline Ion shuttling (QCCD, junctions, grid traps) · alternate ▣ Fig. 1 (repeating 2D grid of unit cells); §II Architecture ✅ Q-Surge (with Riverlane, Bay Photonics) to add 2-D qubit connectivity to QUARTET; no timeline or target published |
| 5 Control | Chip-integrated microwave control (ions) · primary ▣ Fig. 1 (shared current-carrying traces + local tuning electrodes); Fig. 2 (DC electrodes set qubit position); §II Architecture; App. A ✅ chip-integrated electronic (microwave) control; 1Q gate error 1.5e-7 without magnetic shielding per Atlas ct_ionmw attrs, not on the cited page |
| 6 Readout | Fluorescence state detection (ions, defects) · primary ▤ §III Experiments (729 nm shelving, state-dependent fluorescence on a CMOS camera; lasers only in zone 4 for SPAM) 🔎 fluorescence readout; family-determined, no readout fidelity published |
| 7 Code | |
| 8 Decoder | |
| 9 Interconnect | |
| 10 Manufacturing | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) · primary ▤ §II Architecture ('standard microfabrication and packaging processes', 'established foundry processes') 🔎 trap chips from standard semiconductor fabs (Atlas fab_trap attrs); moving to SkyWater in-house |
Standard records
2Q error under full-width parallel operation → 1.00e-4 · best (99.99% two-qubit fidelity)
a hero-pair record, not a system median · Oct 2025 · source
evidence: ✅ 6 / 11