Chip-integrated microwave control (ions) ct_ionmw

The control layer of the laser-free ion machine: the electronics generating the qubit drive, the chip conductors radiating it, and the wiring between. Hyperfine splittings sit at 1–13 GHz, so the wavelength exceeds the whole trap and nothing is focused. Addressing is geometric, via the near field of a trace tens of micrometres from the ion, or spectral, when a static magnetic gradient gives each ion its own resonance. One family descends from NIST Boulder's near-field gates of the early 2010s, carried today by Oxford Ionics inside IonQ; the other is Wunderlich's magnetic-gradient-induced coupling from Siegen, commercialised by eleQtron as MAGIC.

Attributes: carrier affinity 1.0, fully fabricated — the ion is natural, everything this node owns is lithographic; no characteristic time and no entangling action of its own; no readout, fluorescence stays optical; no mobility, the structure is static and ions are transported past it; microwave modality at room-temperature placement, only routing on-chip; Pauli error structure, no leakage channel of its own; MEMS-class manufacturing, a multilayer surface-electrode metal stack. The node dates from 2024, when the sub-part-per-million single-qubit gate D[103] and the first fielded MAGIC demonstrator C[590] arrived.

A 10 GHz photon carries ~40 µeV against an optical Raman photon's ~2 eV. Driving through a virtual excited state costs spontaneous scattering, which floors laser gates near 10⁻⁴ and converts part of that error into leakage; a microwave drive touches no excited state, so the term vanishes. What remains is classical — source amplitude and phase noise, magnetic-field noise, calibration drift — hence a floor of 1.5(4)×10⁻⁷ per Clifford on a ⁴³Ca⁺ clock qubit, T2 ≈ 70 s, at room temperature, unshielded, calibration error below 10⁻⁸ D[103].

The bill arrives in current: spin–motion coupling, the entangling ingredient treated in the sibling gate brief, needs a gradient, and a gradient at the ion means amperes microns away. Three consequences follow. Ohmic dissipation, since the 10 GHz copper skin depth is sub-micrometre and the heat lands in the chip holding the ion; global reach, since every ion sees a drive whose wavelength dwarfs the trap, so selectivity must be built from routing or frequency separation; and drive-induced motional heating, which shows up not as a control error but as a degraded entangling gate later. Superconducting traces and on-chip switching that keeps unselected zones cold would move the floor.

Every record above was taken on one or two ions in a laboratory trap; no public device drives eight or more zones from chip-integrated conductors. The largest ion machine in service, the 98-ion Helios, is laser-driven with 1,228 electrodes and ≥7 wavelengths, and spends ~55 ms per full-width layer on transport, sorting and cooling against a ~70 µs gate D[97]. The dominant Oxford error term is decoherence plus leakage and measurement, not the drive electronics D[103]; at system scale it should be crosstalk and drive-induced heating, neither published.

The chip is an rf circuit that happens to trap ions: metal levels with a top layer sized for ~1 A at gigahertz frequencies, vias moving the DC fan-out off the ion-facing surface, and — in WISE — switching devices integrated in a form "compatible with its fabrication and operation constraints", synthesis left outside S[325]. That is a semiconductor-fab specification, not an optics-shop one, and it explains capital allocation better than any roadmap slide. IonQ bought Oxford Ionics for $1.075 B (closed 2025-09-17) fact, then the 200 mm foundry SkyWater for ~$1.8 B (closed 2026-07-31) fact, while disclosing only a "semiconductor-based approach to manufacturing" C[19]. In Germany the split is contractual: eleQtron builds trap and MAGIC hardware, NXP the control and regulation electronics, ParityQC the architecture layer G[327].

No yield, uniformity or cost-per-qubit figure is public for a microwave trap chip as of 2026-09-03. The one quotable ratio is 0.2 signal sources per qubit at 1,000 qubits S[325], against a laser system's per-zone beam path and ≥7 wavelengths D[97]. Single points of failure sit in trap fabrication — Sandia, Infineon, Honeywell in-house, IonQ's captive SkyWater — not in the commodity microwave chain; export exposure runs through the September 2024 US quantum controls, ECCN unverified.

Per qubit: one tone at 1–13 GHz with sub-milliradian phase control, plus trap DC voltages and a stable magnetic environment. The naive build gives one synthesiser, amplifier and coaxial feedthrough per zone, and it is feedthrough count and heat load, not qubits, that stops the machine at a few hundred. WISE answers with demultiplexing — synthesis at room temperature, simple switches on the chip, one shared high-power signal fanned out to the selected zone — yielding ~200 sources for 1,000 qubits at 40–2,600 layers per second S[325]. That is the move superconducting digital control makes when one digital input feeds several qubits D[304].

At 10³ qubits the binding question is whether an on-chip switch can sit micrometres from an ion without charging dielectrics or adding electric-field noise: unpublished, and the load-bearing unknown here. At 10⁴ the wall is thermal — parallel gates dissipating tens of milliwatts to watts each cannot run together in a 4 K trap with a one-watt cooling budget, so parallelism trades against clock rate, which the record's room-temperature operation avoids at the price of higher anomalous heating D[103]. At 10⁶ nothing published applies; it needs gigahertz synthesis on-chip. Latency stays comfortable: 10–1,000 µs gates leave FPGA control three orders of magnitude of headroom, the inverse of the superconducting case.

The node sits on the architecture Trapped ions — electronic qubit control (laser-free, microwave-driven gates) (IonQ/Oxford Ionics, eleQtron) and is the alternate control of Trapped ions — QCCD (transport between zones) (Universal Quantum). The register lists 8 machines using it, among them JION, QSea I, QUARTET and iQPU / UQConnect. It requires surface-electrode ion-trap microfabrication, specifically the current-carrying traces; it provides the signal sources for the electronic near-field microwave gate; it replaces laser control of ions. The switching price is precise: gate lasers go, but cooling, state-preparation and readout lasers stay, so a "laser-free" machine still carries optics, the trap chip becomes a microwave design problem, and the species choice narrows to hyperfine ions with a usable clock transition. Here a natural carrier is driven by a wholly fabricated control structure — the manufacturing burden moves off the qubit onto the chip around it.

Derived clock = sum of the syndrome round: gate layers + transport + readout + reset: 1.5×10⁻³ s — seven gate layers of today's electronic gate plus readout and reset, no transport — against ~5.5×10⁻² s on a transport-based machine of the Helios type D[97]. Neighbouring empty slots: cryogenic on-chip microwave synthesis; a trap-qualified on-chip current switch with a published electric-field-noise spectrum; superconducting current traces in an ion trap.

The 10⁻⁷ figure is a randomised-benchmarking number whose per-Clifford decay is comparable to slow drift, so it states as much about long-run stability and the leakage and SPAM model as about the gate D[103]. Benchmarking here does not capture spectator crosstalk from the global far field, a.c. Zeeman shifts on neighbours, or drive-induced heating, which surfaces only in a later entangling gate. No simultaneous randomised benchmarking, crosstalk-RB or cycle benchmarking exists for a chip-integrated microwave device, and the 8.4(7)×10⁻⁵ two-qubit result has no independent replication as of 2026-09-03 D[102]. Two source issues: the main report attributes gate durations of 225.8 µs (2025) and ≈120 µs (2024) to a paper whose abstract states neither, so those are carried as reported; and WISE's source count and layer rate are architectural estimates S[325], not measurements.

Not published: Universal Quantum's DLR contract value, funding and 2025–2026 status; the QSea I and QSea II contract values in EUR; patent counts for the three families; and per-qubit cost or yield for microwave trap chips.

Money.

• 2023-03-01 · DLR QCI with eleQtron, NXP, ParityQC · QSea I contract to 2027-02-28 · value not disclosed · active G[327]
• 2024-05-30 · eleQtron, NXP, ParityQC · QSea I demonstrator delivered, Hamburg · no amount · delivered C[590]
• 2025-06-09 · IonQ · M&A, Oxford Ionics · $1.075 B · closed 2025-09-17 fact
• 2025-07-08 / 2025-10-12 · IonQ · equity · $1.0 B then $2.0 B at $93/share · cash $3.0 B, Q2-2026 revenue $80.1 M · closed fact
• 2025-11-06 · DARPA · QBI Stage B incl. IonQ · up to $15 M each · announced fact
• 2026-01-26 · IonQ · M&A, SkyWater · ~$1.8 B ($15.00 cash + 0.4883 shares per share) · closed 2026-07-31 fact
• 2026-05-05 · eleQtron · Series A · €57 M, €54 M backlog · closed C[129]fact

Market & supply chain. The enabling equipment is microwave synthesis and amplification — AWG (arbitrary waveform generator) and direct-digital sources, GaN/GaAs amplifiers, coaxial feedthroughs — a commoditised dual-use base with almost no vendor bargaining power, unlike the narrow-linewidth-laser oligopoly the optical machines need. Concentration risk migrates upstream into multilayer trap fabrication, the segment IonQ has internalised; unit economics are undisclosed. G3 (early fault tolerance) pays through gate fidelity and G7 (deployable systems) through removal of the gate-laser optical table; G4 pays later, G1 and G6 not at all.

IP & standards. The relevant families are Oxford Ionics' electronic-qubit-control filings (Ballance/Malinowski lineage from 2019, now IonQ-assigned), the Siegen magnetic-gradient family behind MAGIC, and Universal Quantum's modular-microwave filings. No dated patent-database query was run, so no count is claimed; no litigation, standard or open-source stack is specific to microwave ion control.

Roadmaps & track record. IonQ (promised 2025-06-13 · for 2026 · 256 qubits at 99.99% · slipped to commissioning H1 2027); IonQ (promised 2025-06-13 · for 2027 · 10,000 physical qubits on one chip · no multi-zone chip-integrated microwave data as of 2026-09-03); IonQ (promised 2025-06-13 · for 2030 · 2 M physical / 40–80 k logical) Rfact; eleQtron with DLR (promised 2023-03 · for year one · a MAGIC demonstrator in Hamburg · delivered 2024-05-30), QSea II (for 2027-02-28 · industry-ready successor · no public target) G[327]C[590]. IonQ's gate physics leads the world and its component claims have held; its scale claims have not, the 2020 roadmap having missed 4,000 qubits by 2026 roughly 40-fold, and the architecture behind the 10,000-qubit promise is still a paper. eleQtron is small and has delivered what it contracted for, where the deliverable was a demonstrator rather than a fidelity record.

Strategic reading. If this works at 10³ ions, value accrues to whoever owns a qualified multilayer trap line plus an rf design team; IonQ has bought both, and NXP gives the European line the same pairing without vertical integration. The losers are the laser supply chain and the integration advantage of the optical incumbents, since Helios's 1,228 electrodes and seven wavelengths do not transfer to a microwave chip D[97]. The substitution threat runs the other way with equal force — laser control has run 98 ions with all-to-all connectivity, microwave control 30, in JION, with no gate fidelity disclosed — so the node trades proven scale for a better error floor and a better wiring asymptote.

Confirm if a device with ≥8 zones driven by chip-integrated conductors is published with simultaneous-RB crosstalk figures before 2027-12, if IonQ commissions 256 qubits at 99.99% in H1 2027 on full-register rather than pairwise benchmarking, or if eleQtron publishes a QSea II fidelity before 2027-02-28. Demote if no multi-zone device appears by end-2027, or if the first one reports drive-induced heating forcing one source per zone, since the wiring advantage then evaporates. Best case by 2029: a 10³-ion register wired by on-chip switching at ~200 sources, two-qubit error near 10⁻⁴, no gate lasers. Worst case: the records stand, the architecture does not, and microwave control survives as the single-qubit layer of an optically entangled machine.

Open questions. (1) How much anomalous heating do drive currents inject at entangling-gate gradients? (2) Can an on-chip switch operate micrometres from an ion without dielectric charging? (3) Room temperature or 4 K, given that lower heating buys no headroom for parallel drive? (4) Does frequency addressing scale past ~10 ions per chain? (5) In a static register, is the derived clock gate- or transport-limited?