IonQ Superion 10K
IonQ Superion 10K
architecture: Trapped ions — electronic qubit control (laser-free, microwave-driven gates) · Open on the map
Register profile — the machine's variant of its architecture
qubit type: trapped-ion qubit (species not stated)
gate mechanism: Electronic Qubit Control (EQC): trapped-ion qubits controlled by electronics integrated on the chip
control: EQC with CMOS integrated onto the trap chip
control placement: on-chip (CMOS integrated on the trap chip)
codes: generalized_bicycle, qcga
flags: a target, not a device
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Trapped atomic ion · primary ▨ EQC paragraph (controls trapped-ion qubits with electronics integrated on the chip) ✅ trapped-ion qubits (species not stated); 10,000-qubit target |
| 2 Encoding | Hyperfine / clock-state qubit · primary ◌ 🔎 hyperfine qubit assumed for electronic control (family-determined; qubit states not stated) |
| 3 Gate mechanism | Electronic microwave gate (ions, laser-free: near-field or static gradient) · primary ▨ EQC and Oxford Ionics paragraphs 🔎 EQC: qubits driven by on-chip electronics (Oxford Ionics technology); gate mechanism for the 10K not detailed |
| 4 Connectivity / transport | — undisclosed — exists, nothing published ▨ 🔎 connectivity of the 10K not published (bus or shuttling) |
| 5 Control | Chip-integrated microwave control (ions) · primary ▨ Superion 10K paragraph (integrates CMOS onto the chip); EQC paragraph ✅ EQC: control electronics integrated on the trap chip; the 10K integrates CMOS onto the chip |
| 6 Readout | Fluorescence state detection (ions, defects) · primary ◌ 🔎 fluorescence state detection (family-determined) |
| 7 Code | Non-local qLDPC codes (bivariate bicycle, 'gross') · primary ▤ abstract; architecture section ✅ GB8 [[102,22,9]] memory, BB7 [[70,6,9]] memory with a magic factory; IonQ's Superion release names the 10K as the first generation built to run Walking Cat (sweep 7 Oct 2026, source read) |
| 8 Decoder | |
| 9 Interconnect | — undisclosed — exists, nothing published ▨ 🔎 platform said to scale from 256 to millions of qubits; the 10K link architecture not described |
| 10 Manufacturing | 300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▨ SkyWater paragraph; Superion 10K paragraph ✅ CMOS integrated onto the trap chip; Superion chips designed and fabricated with subsidiary SkyWater (first 256-qubit QPUs after six tapeouts) Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) · alternate ◌ 🔎 surface-electrode ion-trap chip (family-determined) |
evidence: ✅ 4 / 11