Superion 256

Raveh Neeman

doi:10.5281/zenodo.22674814

IonQ · trapped ions · ANNOUNCED (orderable; first ions trapped in prototypes; deliveries 2027 — NVAQC 2027, FIU late 2027) (8 Sep 2026) · 256 physical qubits · access: orders open; a Superion 256 planned for deployment with an SDT customer in South Korea (announced 21 Sep 2026, no date)

architecture: Trapped ions — electronic qubit control (laser-free, microwave-driven gates) · Open on the map

Register profile — the machine's variant of its architecture

qubit type: hyperfine qubit

gate mechanism: Electronic Qubit Control, chip-integrated electronics rather than lasers

connectivity: chain bus, all-to-all claimed

control: chip-integrated microwave; standard server-rack footprint, less power than a rack of GPUs

control placement: on-chip microwave

readout: fluorescence

gate evidence: no published figure

decoder mode: planned — named in a roadmap only

flags: blueprint not demonstration

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Trapped atomic ion · primary ▤ §II.1 Architecture ✅ 256 ion qubits in a single fully integrated QPU; hyperfine qubit (ANNOUNCED 8 Sep 2026, deliveries 2027)
2 Encoding	Hyperfine / clock-state qubit · primary ◌ 🔎 hyperfine qubit (register); no encoding detail published
3 Gate mechanism	Electronic microwave gate (ions, laser-free: near-field or static gradient) · primary ▤ §II.1 Architecture ✅ Electronic Qubit Control (EQC): chip-integrated electronics rather than lasers
4 Connectivity / transport	Ion-chain motional bus (all-to-all in chain) · primary ▨ 🔎 chain bus, all-to-all claimed; 256 qubits (degree 255)
5 Control	Chip-integrated microwave control (ions) · primary ▨ ✅ chip-integrated microwave control; standard server-rack footprint, no bespoke building work, less power than a rack of GPUs
6 Readout	Fluorescence state detection (ions, defects) · primary ◌ 🔎 fluorescence
7 Code	— undisclosed — exists, nothing published ▨ Superion launch release, 8 Sep 2026 ✅ the release designates no code for Superion 256; the 10K is the first generation built to run the Walking Cat architecture (sweep 7 Oct 2026, source read)
8 Decoder	— undisclosed — exists, nothing published ◌ Part V Architecture 🔎 decoder planned, algorithm not named (IonQ's published single-CPU decoder is a simulation study)
9 Interconnect	Ion–photon link · primary ▨ ✅ Lightsynq photonic interconnect, claimed up to 50× higher entanglement rates; no absolute rate published
10 Manufacturing	300 mm CMOS foundry (spins, cryo-CMOS, superconducting wiring) · primary ▨ ✅ first fully integrated 256-qubit QPUs fabricated at SkyWater (IonQ subsidiary); following generations designed, fabricated and packaged similarly Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) · alternate ◌ 🔎 alternate: integrated ion-trap chip, SkyWater-fabricated

Standard records

qubit·rounds per magic state → 4.00e+7 Toffoli · blueprint, not measured (ECDLP-256 end to end)

19,397 physical ions, 25.7 days, 63% success · Sep 2026 · source

evidence: ✅ 6 / 11