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SFQ digital control (4 K / mK) ct_sfq

Quantised flux pulses from a niobium digital chip flip-chipped onto the qubit die drive gates at millikelvin, replacing per-qubit microwave coax.

SFQ digital control (4 K / mK)

ct_sfq · layer 5 Control · emerging · since 2026
Open on the map

Single-flux-quantum (superconducting-electronics) digital circuits either at the mK stage — pulse trains drive qubits from a flip-chip (1Q > 99 %, 99.9 % peak; nW/qubit claimed) — or at the 4 K stage as an in-fridge controller (DigiQ, 2022: the largest designs fit the few-watt budget of the 4 K stage); the same circuit family loads D-Wave's on-chip flux DACs.

Reading marks
crossing technology — fabricated carrier + control/decoding in the cold stage
Brief →

Key references

[565] R. McDermott and M. G. Vavilov, “Accurate Qubit Control with Single Flux Quantum Pulses,” … · 2014
[304] C. Jordan et al., “A quantum computer controlled by superconducting digital electronics at… · 2026
[56] R. Neeman, “Superconductor Electronics Monitor,” Qodeh, 2026, doi: 10.5281/zenodo.21860767… · 2026
[53] M. Abdel-Kareem, “SEEQC Reports Integrated Qubit Control Logic Operating at Millikelvin Te… · 2026
[249] C. Liu et al., “Single Flux Quantum-Based Digital Control of Superconducting Qubits in a M… · 2023

Design space — attributes

(a) carrier affinity
fabricated
(b) time · entangling
—
(c) readout
—
(d) mobility
—
(e) control
microwave @ 4 K stage / millikelvin stage
(f) error structure
stochastic Pauli
(g) manufacturing
superconducting lithography

Evaluation space — dated attributes

SEEQC mK SFQ control → 1Q > 99%, up to 99.9% (Nature Electronics)
defines: scaling path · 2026-03 · source
DigiQ: A Scalable Digital Controller for Quantum Computers Using SFQ Logic, HPCA 2022 → 4 K in-fridge SFQ controller; the largest designs fit the few-watt budget of the 4 K stage
defines: scaling path · 2022-02 · source
QP-poisoning-limited SFQ MCM → 1.2% error/Clifford, 0.96% from photon-mediated QP
defines: scaling path · 2023-07 · source

SEEQC–IBM integration under DARPA QBI (since Jun 2025).

Standard records

control lines per qubit → not published · typical
SEEQC mK SFQ uses 'digital demultiplexing to distribute control pulses to several qubits, thus breaking the linear scaling' · 2026-03 · source [D] ⓘ

Actors & goals — annotations

Transmon lattice with tunable couplers (alternate) — IBM (Heron, Nighthawk), Google (Willow), Rigetti, IQM, OQC, USTC/Zhejiang, Fujitsu/RIKEN, QuantWare · G2 G3 G4

Edges

needs: Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm)
needed by: Cryogenic / on-chip decoder (cryo-CMOS, SFQ)°
alternatives: Room-temperature electronics + per-qubit coax/flex, Cryo-CMOS controller (4 K / mK)
conflicts with:
Transmon open — no mitigation shown at scale
SFQ switching photons cause quasiparticle poisoning unless shielded (0.96% error source in 2023 MCM)
price photons emitted by switching junctions lie above the aluminium gap (2Δ ≈ 90 GHz) and break Cooper pairs in the qubit film: T1 decay plus correlated, non-Pauli bursts; 0.96(2)% of the 1.2(1)% error per Clifford in the 2023 multi-chip module
mitigation driver on a separate die, pulse-bandwidth limiting (projected 0.1%), quasiparticle traps / gap engineering, mm-wave shielding; SEEQC 2026 reports no detectable poisoning at 5 qubits (press, not independently measured) · 2023-09
Fluxonium open — no mitigation shown at scale
switching photons above 2Δ break Cooper pairs in the junction film — the transmon mechanism, not yet measured on a fluxonium
price inferred from the transmon case: the same aluminium junctions, the same pair-breaking photons; no fluxonium driven by SFQ pulses has been reported, and a fluxonium biased at half flux is less sensitive to quasiparticle tunnelling than a transmon (Pop et al. 2014), so the price may be lower
mitigation as for the transmon: the driver on a separate die, bandwidth limiting, quasiparticle traps, shielding · 2023-09
° one of several that would do · the usual route, not a strict need

Used by 1 machine (1 primary · 0 alternate)

↗ its register card · paper / product / press: links that name the machine (attribution checked on 20 Sep 2026)

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 1(c) — Photograph of the assembled multichip module stack (qubit chip outlined red, SFQ chip outlined blue)
A four-panel paper figure: optical micrographs of a qubit chip (red outline) and a control chip (blue outline), each with a 2 mm scale bar, an oblique photograph of the two dies stacked face to face, and a circuit schematic. It comes from a 2023 arXiv paper by Chuan-Hong Liu et al. (University of Wisconsin-Madison, NIST, Syracuse University). It shows a single-flux-quantum digital driver chip bump-bonded to a two-transmon qubit chip, so control pulses are generated at millikelvin temperature beside the qubits; notice how closely the dies overlap. “Fig. 1(c) — Photograph of the assembled multichip module stack (qubit chip outlined red, SFQ chip outlined blue)” by Chuan-Hong Liu et al. (18 authors, Univ. Wisconsin–Madison, NIST, Syracuse Univ.), arxiv.org/abs/2301.05696, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 3 — Randomized benchmarking of SFQ-based gates at f01/4 = 1.2264 GHz (reference/interleaved pulse sequences)
Three-panel paper figure: drawings of a reference randomized-benchmarking sequence (random Clifford gates ending in a recovery gate) and an interleaved version with a test gate after each Clifford, plus a data plot of sequence fidelity against the number of Cliffords (0-100) with exponential fits. From Chuan-Hong Liu et al. (arXiv, 2023), for a transmon qubit driven by single-flux-quantum (SFQ) pulses instead of microwaves. Notice that interleaved curves decay faster than the reference; the difference measures each gate's error. “Fig. 3 — Randomized benchmarking of SFQ-based gates at f01/4 = 1.2264 GHz (reference/interleaved pulse sequences)” by Chuan-Hong Liu et al., arxiv.org/abs/2301.05696, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
Fig. 1 — Figure 1: Quantum–classical multichip module (MCM). (a) Micrograph of the qubit chip. Two flux-tunable transmons are fabricated on the chip, each wi…
A four-panel paper figure: microscope images of a qubit chip and a single-flux-quantum driver chip (2 mm scale), a photograph of the two chips bonded face to face, and the circuit that links them. It comes from arXiv paper 2301.05696 by Liu, McDermott and co-authors on single-flux-quantum control of superconducting qubits in a multi-chip module. It shows how digital superconducting pulse circuits can sit at millikelvin right next to transmon qubits; notice the bump grids and the small qubit die on the larger control die. “Fig. 1 — Figure 1: Quantum–classical multichip module (MCM). (a) Micrograph of the qubit chip. Two flux-tunable transmons are fabricated on the chip, each with a local…” by Chuan-Hong Liu et al., arxiv.org/abs/2301.05696, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
ct_sfq · layer 5 Control · centrality 14.4 · emerging · since 2026 · updated 2026-09-30

SFQ digital control (4 K / mK)

Quantised flux pulses from a niobium digital chip flip-chipped onto the qubit die drive gates at millikelvin, replacing per-qubit microwave coax.

Verdict. Real: one five-qubit module at 1Q > 99%. Unproven: two-qubit gates, readout, flux bias, robustness to quasiparticle poisoning beyond five qubits. Demote if no >20-qubit SFQ module by 2028.

Key references

Λ = error-suppression factor per code-distance step; QBI = DARPA Quantum Benchmarking Initiative (Stage A concept → B R&D plan → C government V&V); G1–G7 = the report's goal classes (see Actors & economics).

Identity & lineage

Single-flux-quantum (SFQ) logic stores a bit as one flux quantum Φ₀ = h/2e in a superconducting loop; a switching junction emits a pulse of area Φ₀, about 1 mV for 2 ps. Rapid single-flux-quantum (RSFQ; Likharev & Semenov, 1991) logic was built for classical computing at 4 K. For qubit control, a pulse train locked to the qubit period adds coherently into a Rabi rotation S[565]. In the 2026 form the controller is flip-chipped to the qubits at 10 mK D[304]. The wider superconductor-electronics field is tracked in the Superconductor Electronics Monitor P[56].

Attributes. Carrier affinity: fully fabricated control layer. Time / entangling: not applicable. Readout: none demonstrated C[53]. Mobility: none, bump-bonded. Control modality @ placement: microwave drive synthesised digitally at millikelvin. Error structure as the code sees it: Pauli plus correlated poisoning bursts D[249]. Manufacturing: multi-layer niobium lithography.

Physics & limits

Each Φ₀ pulse gives the qubit a fixed phase kick, so gate angle is set by pulse count, not analogue amplitude. Switching costs only ~I_cΦ₀ ≈ 10⁻¹⁹ J per event; within a mixing-chamber budget of tens of µW at 20 mK, RSFQ's static bias power and bias distribution bind first.

The floor is pair-breaking: switching junctions radiate photons above the aluminium gap (2Δ ≈ 90 GHz) that break Cooper pairs in the qubit film — quasiparticle poisoning — causing T1 decay and correlated bursts. Limiting the driver's pulse bandwidth is projected to remove it, bringing gate error toward 0.1% for resonant sequences D[249]. Other levers: quasiparticle traps, gap engineering, millimetre-wave absorbers.

Engineering state of the art

Best demonstrated (3 Sep 2026): SEEQC's five-qubit module at 10 mK, single-qubit fidelity above 99%, one digital input demultiplexed to several qubits D[304]C[53]. No SFQ result exceeds five qubits or includes a two-qubit gate or a QEC cycle.

table
Year Figure Who Tag+key
2014 4,544 on-chip flux DACs for 512 qubits via 56 wires D-Wave D[430]
2019 First SFQ gate on a transmon, ≈ 95% Wisconsin / Syracuse D[566]
2023 Separate-die driver: 1.2(1)% error/Clifford, 0.96(2)% from poisoning Wisconsin, Syracuse, NIST D[249]
2026-03 Five qubits, SFQ control at 10 mK; 1Q > 99%, peak 99.9% SEEQC D[304]
2026-03 Fluxon time-delay readout, no fidelity reported preprint S[568]

Dominant error term: quasiparticle poisoning in the 2023 module D[249]; undisclosed for SEEQC's.

Manufacturing, materials & supply chain

The control die is multi-layer Nb/AlOx/Nb — eight or more planarised niobium layers, 10⁴–10⁶ junctions — unlike the aluminium qubit process D[569]. Foundries are few: MIT Lincoln Laboratory (SFQ5ee line, SQUILL qubit foundry) C[570], AIST's niobium process and cell libraries D[571], and SEEQC's commercial foundry in Elmsford, NY C[572]. Yield needs critical-current spreads of a few per cent across thousands of junctions. Export exposure (BIS rule of 2024-09-06): ECCNs 3A904, 3B904 and 4A906; 3A901.a, read literally, covers cryogenic CMOS only G[301]. Single points of failure: dilution refrigerators, indium-bump bonding, niobium sputter and CMP tools.

Superconductor electronics integrate 1–10 million junctions per cm² against more than 10 billion transistors per cm² in advanced CMOS (figures from the MIT Lincoln Laboratory process papers the authors cite). Design gains such as clock-free xSFQ cells with built-in fan-out amplifiers — 2.7–3.4× fewer junctions on standard benchmark circuits, one cell fabricated in MIT Lincoln Laboratory's SFQ5ee process (critical current density 10 kA/cm²) and verified at 4.2 K — raise functional density, not integration density P[897].

Control, readout & I/O burden

Room-temperature control needs about one drive coax and one flux line per transmon, so fridge cross-section and heat load set its limit; a KIDE-class platform offers > 4,000 rf lines for "over 1000 qubits" Cfact. SFQ control needs a clock plus a low-rate instruction stream D[304]. SFQ readout exists only as a preprint scheme S[568]; SEEQC lists flux bias as future work C[53].

Role in the stack

Architecture: the superconducting transmon lattice. It requires superconducting-qubit lithography and flip-chip modules; it provides cold digital logic for a cryogenic decoder and D-Wave's flux DACs D[430]. The cold routes for control are cryo-CMOS or SFQ: cryo-CMOS reuses commercial foundries and design tools; SFQ needs a niobium ecosystem whose commercial tools stop at physical verification. The conflict with the transmon — switching photons poisoning the qubit — is open: its mitigation is projected D[249], and SEEQC's 2026 report of no detectable poisoning is press coverage C[53]. Contribution to the derived clock: neutral — the syndrome round stays at 0.65 µs against the measured 1.1 µs QEC cycle D[1]. Neighbouring empty slots: SFQ flux bias, SFQ readout.

Evidence — how the numbers were measured

Every headline number is a randomised-benchmarking (RB) Clifford average D[566]D[249]D[304]. RB assumes Markovian, gate-independent errors, so rare correlated bursts average into a slightly worse mean, and a module can pass at 99.9% yet emit correlated errors that decoders do not model. SEEQC's "absence of detectable quasiparticle poisoning" is reported only in press C[53]. Not reported: charge parity under continuous clocking, T1 with the clock on and off. No independent replication: the 2026 authors are all from SEEQC D[304]. Conflicts: "exceeding 99%" in the abstract D[304] against "exceeding 99.5%" in press C[53]; "nanowatts per qubit" C[53] against ~1.6 µW per qubit in a 2026 estimate S[550]fact.

The five-qubit count, 10 mK and "nanowatts per qubit" come from press [53], not from the paper's abstract [304]. SEEQC's S-1 filings give $4.2 M revenue in 2025 and $18.1 M cash at 2026-06-30 fact; its enterprise value comes from trade press. SkyWater's superconducting capability is inferred from mentions in D-Wave's 10-K [492]. Not published: a dated 2025–26 Chinese SFQ qubit-control result, an SFQ-control patent-family count, and SEEQC's offering size (blank in the S-1 amendment of 2026-09-11).

Actors & economics

Who.
Organisation Role Country What they do with it Evidence
SEEQC developer / foundry US mK SFQ control module; commercial Nb foundry D[304]C[572]
IBM integrator US SFQ integration with SEEQC (QBI); own cryo-CMOS control P[54]C[527]
Wisconsin–Madison, Syracuse, NIST Boulder research US Resonant SFQ control; poisoning study S[565]D[249]
MIT Lincoln Laboratory foundry US SFQ5ee process; SQUILL qubit foundry C[570]
D-Wave developer (adjacent) CA On-chip SFQ flux DACs in annealers D[430]
AIST, NEC research / foundry JP Nb cell libraries; 4.2 K multiplexed controller D[571]C[567]

Money.

  • 2020-09-16 · SEEQC · Series A · $22.4 M · EQT Ventures (lead) · closed C[572]
  • 2025-01-16 · SEEQC · growth round · $30 M · SIP Global and others · closed P[573]
  • 2025-06-12 · SEEQC + IBM · SFQ integration under DARPA QBI, IBM the performer G[65] · undisclosed · announced P[54]fact
  • 2026-06-29 · SEEQC · S-1 for a Nasdaq IPO, alongside an Allegro Merger Corp SPAC agreement ($1 B enterprise value) · filed C[556]fact
  • 2026-08-25 · SEEQC / Allegro · SPAC merger ended by settlement: Allegro gets $6 M in stock at a $1.3 B pre-money valuation on a future IPO, sale or ≥ $100 M raise · terminated G[574]

Market & supply chain. No SFQ control market exists yet: one vendor, one demonstration. SkyWater, the merchant foundry named in D-Wave's 10-K filings G[492], has belonged to IonQ since July 2026 C[19]. G3 and G4 pay for it; G7 secondarily.

IP & standards. SEEQC holds the Hypres RSFQ and niobium-process patents, transferred at its 2019 spin-out C[572]. No SFQ-control standards exist; shared design bases are AIST's cell library D[571] and MIT-LL's kits C[570].

Roadmaps & track record. SEEQC: millikelvin SFQ control (promised 2021–22 · delivered 2026-03 at five qubits) D[304]; on-die flux control and readout (announced 2026-03 · undated) C[53].

Strategic reading. Niobium process capability sits with SEEQC and, via Lincoln Laboratory, the US government. Of the cold routes, cryo-CMOS or SFQ, cryo-CMOS has the stronger record: a QEC demonstration under a 4 K cryo-CMOS controller D[190] and parity with warm electronics on an IBM processor C[527]; SFQ has single-qubit gates on five qubits from one group D[304].

Outlook & open questions

Confirm if by end-2027 a group publishes an SFQ-driven two-qubit gate below 1% error, an SFQ-controlled device above ten qubits, or hours of charge-parity data free of clock-correlated bursts. Demote if by end-2028 no SFQ module exceeds twenty qubits, or a decomposition shows poisoning above 0.1% per Clifford. Open questions: does "no detectable poisoning" survive continuous clocking at QEC duty cycles? Can SFQ flux bias hold the DC stability transmons need?

References
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