SEEQC SFQ-controlled 5-qubit system

Raveh Neeman

doi:10.5281/zenodo.22674814

SEEQC

SEEQC SFQ-controlled 5-qubit system

SEEQC · superconducting circuits · DEMONSTRATED (Mar 2026) · 5 physical qubits · access: lab-only

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: transmon

gate mechanism: no entangling gate published under SFQ control; single-qubit charge control by SFQ digital pulse trains

connectivity: not published

control: Single Flux Quantum digital logic co-located with the qubits at 10 mK; integrated digital demultiplexing so several qubits share one control pathway; ~1 nW per qubit

control placement: SFQ at mK

readout: dispersive

gate evidence: no published figure

flags: 1q only

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▤ Supp. §A Device Design and Fabrication; Fig. 1 (system-level overview) ✅ transmon; 5 physical qubits (Mar 2026)
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to \|2⟩ is the price.
3 Gate mechanism	— undisclosed — exists, nothing published ▣ Fig. S2 (2Q Gate Results); Supp. §I 2Q Calibration and Benchmarking ✅ no entangling gate published under SFQ control; single-qubit charge control by SFQ pulse trains, 1Q >99.5%, peaks >99.9% (Mar 2026)
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▤ Supp. §A Device Design and Fabrication (centre qubit capacitively coupled to 4 outer qubits); Fig. S1 (Experimental Diagram) ✅ connectivity not published; 5-qubit system
5 Control	SFQ digital control (4 K / mK) · primary ▣ Fig. 1 (RT vs 4K cryo-CMOS vs integrated SFQ control); Fig. 3 (SFQ demultiplexer); Fig. S3 (SFQ Circuit Schematics); §Demultiplexer (DMX) Results; §Power Dissipation ✅ SFQ digital logic co-located with qubits at 10 mK; digital demultiplexing, <1 line per qubit; ~1 nW per qubit; no detectable quasiparticle poisoning (Mar 2026)
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ▤ Supp. §B Experimental Setup; Fig. S1 (Experimental Diagram) 🔎 dispersive; digital on-die readout is a stated next milestone
7 Code	— none — nothing in this layer ▨ 🔎 no QEC code run (L0)
8 Decoder	— none — nothing in this layer ▨ 🔎 no decoder (no QEC)
9 Interconnect	Multi-die packaging in one module (flip-chip, bump-bonded control die) · primary ▤ Supp. §A Device Design and Fabrication ✅ flip-chip: 5×5 mm quantum chip bump-bonded (indium on an Al hard stop, 10 µm gap) to a 10×10 mm carrier chip with all passive wiring and SFQ elements; signals couple across the vacuum gap
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▤ Supp. §A Device Design and Fabrication (SEEQC SFQuClass Nb process, 1 kA/cm2 JJs, high-kinetic-inductance layer) ✅ Superconducting-qubit lithography (Nb/Al JJ, 300 mm) — IBM Albany 300 mm / Anderon foundry; Google Santa Barbara; Rigetti ABAA trimming (97.4% frequency-targeting success); OQC 500-qubit wafer-scale…

Standard records

control lines per qubit → 1 lines/qubit · best (digital demultiplexing at mK; exact ratio not published)

power ~1e-9 W per qubit at mK · Mar 2026 · source

evidence: ✅ 6 / 10

Pictures

Every picture carries the story of what it shows and its credit line.

A four-panel paper figure: optical micrographs of a qubit chip (red outline) and a control chip (blue outline), each with a 2 mm scale bar, an oblique photograph of the two dies stacked face to face, and a circuit schematic. It comes from a 2023 arXiv paper by Chuan-Hong Liu et al. (University of Wisconsin-Madison, NIST, Syracuse University). It shows a single-flux-quantum digital driver chip bump-bonded to a two-transmon qubit chip, so control pulses are generated at millikelvin temperature beside the qubits; notice how closely the dies overlap. “Fig. 1(c) — Photograph of the assembled multichip module stack (qubit chip outlined red, SFQ chip outlined blue)” by Chuan-Hong Liu et al. (18 authors, Univ. Wisconsin–Madison, NIST, Syracuse Univ.), arxiv.org/abs/2301.05696, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)

Fig. 1 — System level overview external image — opens at the source

Five-panel paper figure mixing renders, circuit diagrams, a photograph and a false-coloured chip image, from a 2026-03-10 journal paper by Caleb Jordan, Jacob Bernhardt, Joseph Rahamim, Alex Kirichenko and 15 others (Seeqc). It presents a five-qubit transmon processor controlled by single-flux-quantum digital circuits, flip-chip bonded onto a carrier chip in one multi-chip module at millikelvin temperature. Panel (a) contrasts room-temperature, 4 K cryo-CMOS and millikelvin control; placing control next to the qubits cuts the wiring leaving the cryostat.

SEEQC Reports First Quantum Computer with Integrated Qubit Control on a Chip at Millikelvin... external image — opens at the source

The video was not opened, so no frame of it has been seen and it is described from its record. It is a BusinessWire video on YouTube (2026) titled 'SEEQC Reports First Quantum Computer with Integrated Qubit Control on a Chip at Millikelvin...', recorded as covering SEEQC's five-qubit module controlled by single-flux-quantum (SFQ) logic. The idea is to generate qubit control signals with superconducting digital circuits at millikelvin temperatures, next to the qubits, instead of routing them from room-temperature electronics.