Multi-die packaging in one module (flip-chip, bump-bonded control die) ic_multidie

Two superconducting dies face each other across a vacuum gap, joined by indium bumps: one carries the qubits, the other wiring, resonators, another material or control logic — the interconnect below the module scale, with no coherent link leaving the package. Sycamore used "indium for bump-bonds between two silicon wafers" D[291]; Zuchongzhi 3.0 puts 105 qubits and 182 couplers on one sapphire chip, "all the control lines and readout resonators" on the other D[35]; Ocelot bonds an aluminium junction die to a tantalum resonator die D[80]; SEEQC sets a 5 × 5 mm qubit chip on a 10 × 10 mm SFQ die D[304]. Root: MIT Lincoln Laboratory's 2017 flip-chip of flux qubits onto a readout-and-control chip D[754]. Not ic_mcm, which tiles qubit dies into one lattice, nor ct_vio, which brings lines through the chip face.
Attributes: fabricated, static; microwave at millikelvin; coherent error; superconducting lithography.

The gap is a circuit element. Coherence survives a cap — bonded flux qubits kept T1 20.9 µs, T2,echo 24.6 µs with galvanic, capacitive and inductive coupling between chips D[754]; transmons at (7.8 ± 0.8) µm average above 90 µs D[755] — but frequencies follow the spacing: 1 µm moves a 6 GHz resonator ~2%, ~120 MHz D[755]. With f ∝ C^−1/2, a cap holding a fraction p of a transmon's capacitance shifts f by ≈ ½p·δd/d — for p = 0.2 and ±0.8 µm on 7.8 µm, ~50 MHz at 5 GHz S; hence SEEQC's aluminium hard stop fixing 10 µm D[304]. Facing ground planes form a parallel-plate guide with lateral modes near c/2L ≈ 7.5 GHz on a 20 mm die, unless ground bumps stitch them at millimetre pitch S.
Bumps. In on a TiN barrier over aluminium is superconducting throughout (Tc 1.1 K), mean critical current 26.8 mA, robust under shear and thermal cycling D[756]. Loss sits at interfaces: electroplated-In transmons reach Q ≈ 10⁶ (T1 ≈ 32 µs at 5 GHz S), most likely limited by the gold contact layer D[757]. Mismatch shears a bump ∝ Δα·ΔT·r/h (r from die centre, h bump height): nil for like substrates, worst for unlike pairs and large dies S.
Quasiparticles. A separate control die cuts the phonon path: an SFQ die on In bumps reached 1.2(1)% error per Clifford, tenfold better than earlier SFQ control D[249]; SEEQC's aluminium-rich bumps double as quasiparticle traps D[304].

The dominant term is the partition the bump permits: Zuchongzhi 3.0 splits tantalum and aluminium between its sapphire chips, which "enhances the relaxation time" D[35]; Ocelot puts junctions, transmons, couplers and buffers on aluminium, storage, readout and Purcell resonators on tantalum D[80].

One process family: In bumps on a TiN barrier D[756], 8 µm pillars at Chalmers D[755], In on an aluminium hard stop at SEEQC D[304], electroplated In that needs gold and pays in loss D[757]; Si–Si at Google D[291], sapphire–sapphire at USTC D[35]. Vias join when lines must leave: MIT Lincoln Laboratory's 10 × 20 × 200 µm superconducting TSVs carried control and readout in a bump-bonded stack D[540]; IBM's Eagle bonds a qubit wafer to an interposer with three-level wiring and through-substrate vias C[758]. No source opened names a bonding supplier or cycling yield, as of 2026-09-26.

A second die moves the wiring wall, not the line count. With k lines per qubit and c per inter-qubit gap, edge routing of an m × m lattice closes at m = 4c/k (the ct_vio estimate); as N = m², doubling c quadruples the ceiling, but lines still leave through a perimeter ∝ √N — only vias or cold control remove that S. The exception is a die that makes pulses: SEEQC's SFQ die demultiplexes so qubits share lines, 2.375 nW per qubit at 1:8 against 5.5 nW for the paper's rf case and 2.5 µW for cryo-CMOS, with "no signal delivery through bump bonds" — all coupling crosses the vacuum gap D[304]. At 10³ qubits a routing die is necessary, not sufficient; at 10⁴–10⁶ it is the substrate for vias or cold logic S.

An alternate in slot 9 of "Transmon lattice with tunable couplers", "Bosonic cavity qubits — cat and GKP" and "Dual-rail erasure qubits". It requires fab_sc ("bump-bonded superconducting dies"); no provides edge is recorded; the graph has ic_mcm replace it ("module-to-module vs die-to-die"), yet both use one bump process and a tiled processor can stack each tile — a boundary, not a substitution S. It sits under ct_vio: a stack exits at its edge unless vias pierce it. Twelve register machines carry it (12 as primary). ✅: Sycamore-53 D[291], Zuchongzhi 3.0 D[35], Ocelot D[80], SEEQC on its Supp. §A D[304], IBM Quantum Eagle r1-r3 C[758], WACQT quantum computer (Chalmers 25-qubit flip-chip processor; 2,900 indium bumps between its two tiers Dfact), SUSTech's four-dual-rail-qubit processor, a qubit chip flip-chipped onto a carrier chip D[406], and Alice & Bob's planned Lithium, "qubits packed on one side and their connections printed on the other" Rfact. The 72-qubit Sycamore stays 🔎 — its paper names no bump, flip-chip or package D[602]; Tianyan-287 inherits by resemblance, a "Zuchongzhi 3.0-like" processor C[708], and Alice & Bob's Beryllium by succession from Lithium, its source not restating the flip-chip; Academia Sinica's "chip-stacking methods" C[759] and Kaveri's "flip-chip integrated technology" P[760] name no bumps; Zuchongzhi 3.2's source was not opened. Gap G-multidie, answered: all seven ✅ carriers document a two-die stack, each partitioned by function or material, none tiling a lattice; the ledger's dual-rail placement is carried by the SUSTech processor.

Coherence under a cap is shown at few-qubit scale D[754]D[755]; stack gate data are small: CZ (98.66 ± 0.08)% D[755], single-qubit fidelity to 99.9% under SFQ control D[304]. Large carriers' benchmarks hide the package. Missing as of 2026-09-26: one design measured with and without a cap; gap maps across a >100-qubit die against frequency-targeting error; bump continuity over thermal cycles; a control figure for Zuchongzhi 3.0's T1 gain.

Tianyan-287's abstract names no packaging, and Zuchongzhi 3.2's packaging is unconfirmed. Shih et al.'s T1 ≈ 32 µs assumes a 5 GHz qubit frequency, which the source does not give. Not published: bump yield or thermal-cycle failures for any carrier machine; the one bump count is the WACQT processor's 2,900, whose inter-chip gap was checked by electron microscopy but not reported fact.

Money. No dated, sourced financial item specific to multi-die packaging was found as of 2026-09-26.

Market & supply chain. Every documented stack is built by its processor's developer or lab S. Pays into G2–G4 on the transmon architecture, G3–G4 on the cat and dual-rail architectures.

IP & standards. No patent count from a named database is given here; no source opened names a bonding standard, as of 2026-09-26.

Roadmaps & track record. No carrier publishes a dated packaging milestone as of 2026-09-26; Academia Sinica "continues to enhance chip-stacking methods" C[759]; Kaveri targets ~100 µs coherence and ~10⁻² error P[760].

Strategic reading. Documented large transmon lattices — Sycamore, Zuchongzhi 3.0, Eagle — route through a second die; it buys materials freedom and routing, not scale. Value moves to gap control and bump yield at 10³–10⁴ bumps and, for SFQ, to the one second die that removes lines.

Confirm if, by 2027-12-31, a carrier above 100 qubits publishes bump count, gap spread and frequency-targeting error; demote if no carrier above 100 qubits publishes those numbers by then. Open questions. (1) What is bump continuity per thermal cycle at 10⁴ bumps? (2) How much fixed-frequency targeting error is gap non-uniformity? (3) Does the bump interface set a loss floor near Q ≈ 10⁶? (4) Can an SFQ die under the qubits keep its error contribution below 10⁻³? (5) Do Sycamore's successors, Zuchongzhi 3.2 and Tianyan-287 keep the two-die stack the register infers?