Sycamore
Sycamore
Register profile — the machine's variant of its architecture
qubit type: frequency-tunable transmon (asymmetric SQUID, Al junctions)
gate mechanism: 86 tunable couplers; native iSWAP-like fSim, 12 ns; 1Q 25 ns
connectivity: square lattice, degree 4
control: 277 DACs (14-bit, 1 GS/s) at room temperature
control placement: room-temp
readout: frequency-multiplexed dispersive
gate evidence: a published figure (source class not yet tagged)
codes: css_4_1_2, quantum_repetition, rotated_surface, surface
flags: claim later eroded
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 bare transmon two-level subspace; no encoding beyond the physical qubit |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▣ Fig. 1a (couplers, blue); Fig. 3b (1Q/2Q gate control waveforms); SI §II (88 adjustable couplers) ✅ 86 tunable couplers; iSWAP-like fSim, ~20 MHz on resonance for 12 ns + CPhase; 1Q 25 ns; 2Q Pauli 0.36% isolated, 0.62% simultaneous |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▣ Fig. 1a (rectangular array, each qubit coupled to four nearest neighbours) ✅ square lattice, degree 4; 53 operational qubits, 86 couplers |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▣ SI Fig. S2 (control electronics, DAC module); Fig. S3 (cryogenic wiring); Fig. S4 (chassis); SI §III.1 ✅ 277 DACs (14-bit, 1 GS/s) at room temperature; ≈5.2 lines per qubit (53 q) |
| 6 Readout | Dispersive microwave readout (+TWPA, Purcell) · primary ▣ SI Fig. S2c (readout chain: AWG, amplification, IF mixing, ADCs); SI §III.2 Readout ✅ frequency-multiplexed dispersive readout |
| 7 Code | Error-detection codes ([[4,2,2]], d=2 surface, iceberg, spacetime) · primary ▤ abstract; Fig. 4 ✅ repetition codes d=3–11 for 50 rounds (exponential suppression); d=2 surface code [[4,1,2]] run as error detection (sweep 7 Oct 2026, source read) |
| 8 Decoder | |
| 9 Interconnect | Multi-die packaging in one module (flip-chip, bump-bonded control die) · primary ▤ §Building a high-fidelity processor (indium bump-bonds between two Si wafers); SI Fig. S1 (packaged chip) ✅ one qubit die + control die, flip-chip with indium bump-bonds between two silicon wafers; no inter-module interconnect |
| 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▤ §Building a high-fidelity processor (Al metallization + JJs, indium bump-bonds); SI §II Fabrication and layout ✅ Al Josephson junctions; two-wafer flip-chip with indium bump-bonds (packaging lineage Google still uses) |
Standard records
2Q error under full-width parallel operation → 6.20e-3 · typical (0.62% simultaneous)
Oct 2019 · source
control lines per qubit → 5.2 lines/qubit · typical (277 DACs / 53 q)
2019 · source
1Q gate time → 25 ns · best
Oct 2019 · source
evidence: ✅ 8 / 10
Pictures
Every picture carries the story of what it shows and its credit line.
