QpiAI Kaveri
QpiAI Kaveri
Register profile — the machine's variant of its architecture
qubit type: transmon in a grid layout
gate mechanism: tunable coupler (assumed); wafer-scale fabrication and flip-chip integration
connectivity: grid
control: room-temperature RF
control placement: room-temp
readout: dispersive
gate evidence: a published figure (source class not yet tagged)
flags: aggregate error only
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to |2⟩ is the price. |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▨ 🔎 tunable coupler (assumed); error rates ≈10⁻² with no 1Q / 2Q / readout breakdown (Feb 2026) |
| 4 Connectivity / transport | |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▨ 🔎 room-temperature RF (register); control circuitry separated from qubit plane by low-loss interconnect layers |
| 6 Readout | |
| 7 Code | |
| 8 Decoder | |
| 9 Interconnect | Multi-die packaging in one module (flip-chip, bump-bonded control die) · primary ▨ 🔎 flip-chip integration: low-loss interconnect layers separate qubit plane from control circuitry inside one module |
| 10 Manufacturing | Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▨ 🔎 wafer-scale fabrication and flip-chip integration; fabricated in India with some imported components |
Standard records
T1 relaxation → 100 µs · scope unstated (best or median not distinguished)
Feb 2026 · source
evidence: ✅ 1 / 10