Sycamore-class 72-qubit processor
Sycamore-class 72-qubit processor
Register profile — the machine's variant of its architecture
qubit type: frequency-tunable transmon
gate mechanism: tunable coupler CZ, 34 ns; 1Q 25 ns; reset 160 ns; full QEC cycle 921 ns
connectivity: square lattice, degree 4
control: room-temperature DACs
control placement: room-temp
readout: dispersive, 500 ns measurement
gate evidence: no published figure
decoder mode: offline — syndromes decoded after the run
codes: quantum_repetition, twist_defect_surface, xzzx
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 bare transmon two-level subspace; no encoding beyond the physical qubit |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▣ Fig. 1b (stabilizer circuit, CZ gates); Fig. 1c (CZ error CDF) ✅ tunable-coupler CZ 34 ns; 1Q 25 ns; reset 160 ns; full QEC cycle 921 ns (2022) |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▣ Fig. 1a (square-lattice layout); Fig. 1b (four NN CZs) ✅ degree-4 square lattice, 72 transmons + 121 tunable couplers |
| 5 Control | |
| 6 Readout | Fast unconditional / dissipative qubit reset · primary ▣ Fig. 1b (MR step, 921-ns cycle budget); Fig. 4a (measure+reset error) ✅ reset 160 ns as a QEC-cycle budget line item (no technology); 500 ns measurement within 921 ns cycle Dispersive microwave readout (+TWPA, Purcell) · alternate ▣ Fig. 1b (measure and reset); Fig. 1c (Meas. error CDF) ✅ dispersive readout, 500 ns measurement (2022) |
| 7 Code | Rotated surface code (+ yoked variants) · primary ▣ Fig. 1a (d=5 code); Fig. 3 (logical error d=5 vs d=3); Fig. 4b (repetition) ✅ rotated/XZZX surface: d=5 2.914(16)% vs d=3 3.028(23)% logical error/cycle, Λ₃/₅ ≈ 1.04; d=25 repetition floor 1.7e-6/round |
| 8 Decoder | MWPM / Sparse Blossom (+ correlated matching) · primary ▤ §Decoding and logical error probabilities ✅ matching / tensor-network decoding, offline Neural decoders (AlphaQubit 2, CNN, transformers) · alternate ▤ 🔎 AlphaQubit neural decoder trained on this device's d=3/d=5 data; offline — none — nothing in this layer ▤ §Decoding and logical error probabilities 🔎 decoding offline only (matching / tensor-network, AlphaQubit); no in-loop deployment |
| 9 Interconnect | Multi-die packaging in one module (flip-chip, bump-bonded control die) · primary ◌ 🔎 single processor module in the Sycamore flip-chip lineage; no inter-module interconnect |
| 10 Manufacturing |
Standard records
correlated-burst rate → 1.70e-6 per round · typical (d=25 repetition floor; 1.6e-7 excluding one high-energy event)
2022 · source
idle / memory error per round → 0.0291 · typical (logical error per cycle at d=5)
2022 · source
reset / initialisation time → 160 ns · typical
2022 · source
evidence: ✅ 7 / 13
Pictures
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