XAPHIRO (QUDORA 50-qubit NFQC prototype for the DLR Quantum Computing Initiative)
XAPHIRO (QUDORA 50-qubit NFQC prototype for the DLR Quantum Computing Initiative)
architecture: Trapped ions — electronic qubit control (laser-free, microwave-driven gates) · Open on the map
Register profile — the machine's variant of its architecture
qubit type: hyperfine qubit
gate mechanism: Near-Field Quantum Control microwave gates; CMOS-compatible manufacturing
connectivity: not published
control: chip-integrated microwave near-field control (NFQC); trap at 4 K in a cryostat; NXP CMOS photon detector
control placement: on-chip microwave
readout: fluorescence
gate evidence: no published figure
flags: no hardware, source seen as a snippet only, source not confirmed
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Trapped atomic ion · primary ▣ Fig. 2 (energy levels of 9Be+ at 22.3 mT); §Results and discussion ✅ hyperfine ion qubit; emulator only, no hardware results |
| 2 Encoding | Hyperfine / clock-state qubit · primary ▣ Fig. 2 (9Be+ hyperfine levels; field-independent |1,1>-|2,1> qubit at 22.3 mT) ✅ hyperfine qubit (family-determined) |
| 3 Gate mechanism | Electronic microwave gate (ions, laser-free: near-field or static gradient) · primary ▣ Fig. 1 (electrode configuration with embedded microwave conductor); Fig. 3 (parity oscillation of entangled state) ✅ Near-Field Quantum Control microwave gates |
| 4 Connectivity / transport | |
| 5 Control | Chip-integrated microwave control (ions) · primary ▣ Fig. 1 (electrode configuration around the trap centre, integrated microwave conductor) ✅ chip-integrated microwave; on-chip microwave |
| 6 Readout | Fluorescence state detection (ions, defects) · primary ▤ §Results and discussion (fluorescence detection on the closed-cycle transition, 400 µs) ✅ fluorescence (family-determined) |
| 7 Code | |
| 8 Decoder | |
| 9 Interconnect | |
| 10 Manufacturing | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) · primary ▤ §Results and discussion (trap fabricated at PTB cleanroom, single-layer method, AlN substrate, ~10 µm Au, 5 µm gaps) ✅ CMOS-compatible manufacturing of the NFQC trap chips |
evidence: ✅ 6 / 10