Helix architecture on Helios
Helix architecture on Helios
Register profile — the machine's variant of its architecture
qubit type: hyperfine clock qubit (Helios hardware)
gate mechanism: transversal logical Cliffords in depth 1; automorphism gates are free because QCCD transport relabels qubits in software
connectivity: all-to-all by transport
control: Helios control stack; Adaptive Syndrome Extraction cuts gates 33% and time 23%
control placement: room-temp + in-trap optics
readout: fluorescence
gate evidence: a published figure (source class not yet tagged)
decoder mode: offline — syndromes decoded after the run
codes: c4_helix, rotated_surface, toric
flags: architecture not machine, code id missing in the register, a component, not a machine
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Trapped atomic ion · primary ▤ 🔎 Helios hardware ¹³⁷Ba⁺ hyperfine clock qubits; Helix is a QEC architecture + code, not a separate machine |
| 2 Encoding | |
| 3 Gate mechanism | Mølmer–Sørensen / light-shift laser gate · primary ▣ Fig. 2 (logical randomized Clifford benchmarking); Fig. 4 (logical gates); §II.B; App. A.1 ✅ full two-qubit logical Clifford group in depth-1 transversal gates; logical Clifford error 2.8×10⁻⁴, 4.28× better than the physical gate (Sep 2026) |
| 4 Connectivity / transport | Ion shuttling (QCCD, junctions, grid traps) · primary ▣ Fig. 4 (SWAP-transversal logical gates); App. A.1 Logical Clifford gates ✅ all-to-all by transport (degree 97); software qubit relabelling + ion transport make automorphism gates free |
| 5 Control | Laser control with integrated photonics (ions) · primary ▣ Fig. 13 (adaptive vs nonadaptive syndrome extraction); App. A.2.a Adaptive syndrome extraction ✅ Helios control stack; Adaptive Syndrome Extraction cuts gates 33% and time 23% |
| 6 Readout | |
| 7 Code | High-rate concatenated codes with transversal gates · primary ▣ Fig. 1a (schematic of [[10,2,3]] and [[20,2,6]] C4-Helix codes); §II.A; App. A; Fig. 8 ✅ [[20,2,6]] C₄-Helix = [[10,2,3]] twisted toric ∘ [[4,2,2]]; 52 physical → 2 logical; 4.6×10⁻⁵ per logical qubit per cycle; 3.5× saving vs rotated surface code |
| 8 Decoder | — (Atlas gap: ∅G-frontier) · primary ▤ App. C.2 Frontier decoding and confidence-based postselection; Fig. 12 caption ✅ Frontier: block-specific offline decoder for concatenated high-rate codes, neither matching, BP-class nor GPU-platform; streaming version is future work |
| 9 Interconnect | — none — nothing in this layer ◌ 🔎 n/a — code architecture run on single-module Helios; no interconnect |
| 10 Manufacturing | Ion-trap fabrication (surface-electrode chips; machined 3D blade traps) · primary ◌ 🔎 Helios surface-electrode trap (in-house microfabrication) |
Standard records
acceptance fraction → 0.995 · best (0.5% forced-gap discard)
Sep 2026 · source
idle / memory error per round → 4.60e-5 · best (per logical qubit per cycle, no post-selection)
9.3e-5 per round for the 2-logical block · Sep 2026 · source
evidence: ✅ 5 / 10
Pictures
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