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Continuous-variable photonic — GKP on the map bar: Optical GKP

Continuous-variable photonic — GKP

architecture · ph_cv · 10 layers · 14 technologies counting alternates

Actors & goals

Xanadu (Aurora)
goals: G4 G6

Derived clocks

syndrome round
—
measured cycle
1 MHz clock (Aurora); no logical cycle
reaction time
1.0 µs (published loop) · floor 2.0 µs
coherence
T1 — · T2 — · ops per coherence —
idle exposure per round
t_round/T2 = — · measured idle error —
notes
measurement-driven photonic architecture: no syndrome round; native clock in the measured column; reset time unpublished for ro_homodyne; no code on this architecture
t_round = d₂·(t_2Q + t_move) + d₁·t_1Q + t_meas + t_reset — a sum of the round's phases, from the code node, the attributes and the standard records; the measured cycle is the check.

Relations within the architecture

→ dependencies · 17
SNSPD / TES is needed by Fusion
Squeezed mode is needed by GKP grid (or an alternative)
PIC foundry is needed by EO drive + feed-forward (or an alternative)
GKP grid is needed by Bosonic concatenation (or an alternative)
qLDPC (gross) is needed by Relay-BP
PIC foundry is needed by Squeezed mode (or an alternative)
Bosonic concatenation is the usual route for MWPM / Blossom (or an alternative)
Squeezed mode is needed by SNSPD / TES (or an alternative)
Photonic switching is needed by qLDPC (gross) (or an alternative)
Squeezed mode is needed by Fusion (or an alternative)
✕ conflicts · 2
qLDPC (gross) conflicts with MWPM / Blossom · bypassed by choosing another technology in place of one of the two
Squeezed mode conflicts with Photonic switching · open — no mitigation shown at scale
⇄ alternatives · 3
Fusion alternative to CV Gaussian
MWPM / Blossom alternative to Relay-BP
SNSPD / TES alternative to Homodyne (CV)

Reading

hatched (crossing): Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm)
∅ empty slots: —

Machines of this architecture · 1

↗ its register card · paper / product / press: links that name the machine (attribution checked on 20 Sep 2026)

The architecture in the report (§8.3)

8.3.11 Optical GKP — Continuous-variable photonic — GKP (ph_cv)

The idea. Squeezed light modes (squeezed), not single photons, carry the computation: beamsplitters entangle them deterministically into a time-multiplexed cluster state, CV Gaussian gates (g_cv) compute on it by homodyne measurement and feed-forward, and GKP grid encoding (enc_gkp) supplies both the qubit and the non-Gaussian resource that Gaussian operations lack. Xanadu's blueprint builds "three-dimensional hybrid resource states comprising both bosonic qubits and squeezed vacuum states" [S][267]. Against fusion it trades probabilistic entangling for deterministic, and heralded erasures for analogue noise: loss acts as a random displacement that spends squeezing. The bet: photonic chips will make GKP states near the ~10 dB of squeezing the code needs before loss consumes them [S][174].

What it needs. Gaussian gates require squeezed modes and room-temperature feed-forward; homodyne readout requires a local oscillator phase-locked by the same electronics, so detection, decision and modulation must close inside the 1 µs clock [D][173]. Optical GKP requires that squeezing; the best on-chip GKP source reaches 0.62 dB effective [D][174]. The code, bosonic concatenation with GKP under an outer qLDPC code, requires the GKP inner qubit, so it waits on that gap. Seven layers hold one technology each. The replaces edges fix the architecture's identity: Gaussian gates against fusion, homodyne against photon counting, Relay-BP against matching.

Where it stands. One machine, one device: Aurora (Xanadu, January 2025), 35 chips, 12 modes per 1 MHz cycle, a 12×N cluster state generated for two hours at ~14 dB total loss, no error-corrected computation [D][173]. It runs the only in-loop decoder in photonics, within the 1 µs clock [D][173], and 11 of its 12 cells are documented, the best-evidenced photonic machine. Table 8.3 still credits the architecture with no gate-capable device and no two-qubit error; the register flags Aurora detection-only and loss-dominated. Xanadu puts its loss 24× above threshold in 2026 [C][178] and plans 1× in 2030, a fault-tolerance milestone in 2028–29 and 1,000+ logical qubits by 2031 [R][178]; it holds a DARPA QBI Stage B slot [65], [66].

Exceptions and borrowings. An architecture of one machine cannot show whether it is drawn well; it is drawn around one design. Aurora fits every slot, with no gap and no none, but its alternates amend the edges. Number-resolving detection heralds its GKP states, so the architecture needs both detector technologies its replaces edge treats as rivals: counting to make the qubit, homodyne to compute. Its decoder is matching, with Relay-BP, the architecture's primary for the qLDPC outer code, as alternate. The gate alternate, fusion, has no machine. Jiuzhang 4.0 and Borealis, Aurora's predecessor, share the squeezed carrier and hold the Gaussian-gate technology as an off-architecture alternate without feed-forward: a Gaussian sampler is this architecture minus feed-forward and GKP states. Encoding and code are shared with the microwave cat-and-GKP architecture.

The next test. By March 2028 (§5.2): an on-chip optical GKP state above 1 dB effective squeezing, and a published loss factor within 10× of threshold; Xanadu's own schedule, 24× in 2026 to 1× in 2030, needs a gain of ~2.2× a year [S]. Both would keep the 2028–29 milestone credible. Demote if effective squeezing stays below 1 dB through 2027, or the milestone moves.

What the builders say. Xanadu chose GKP qubits because their logic runs by deterministic, room-temperature techniques and the states travel between chips over standard fibre [C][856]. It says Aurora could in principle grow to thousands of server racks and millions of qubits [C][857], and names optical loss as the next hurdle [C][856]. Its August 2026 roadmap cuts a 'key loss technical indicator', which it does not define, from 24.1× in 2026 to 1.0× in 2030 [R][178]; its chief executive expects fault tolerance in 2028–29 [R][178]; and it promises up to 200 logical qubits by 2029, 500 by 2030 and over 1,000 by 2031 [R][178].

Machines of this architecture (register: 1, of them 1 devices, 0 gate-capable). Xanadu — Aurora (demonstrated, 12).

Cells outside the architecture's slots: none — every cell of every machine sits in a slot of the architecture.