Electro-optic drive + feed-forward electronics (room temperature) ct_eo

The 300 K layer that drives photonic qubits and closes the measurement loop: pump lasers, thin-film lithium-niobate (TFLN) or barium-titanate (BTO) modulators, and electronics turning a detector click or homodyne quadrature into a drive voltage before the next photon arrives. Alone among control nodes it has no cryogenic variant: electronics at 300 K read detectors near 2 K, so every loop crosses that boundary twice. Attributes: no carrier of its own, immobile, loss-dominated error; electro-optic modality at room temperature, photonic-IC fabrication.

Modulator bandwidth is not the constraint. What binds is detector rise, discrimination, decision and driver settling, which must fit inside optical delay you can afford. Holding a photon 100 ns in silicon nitride costs ~15 m of waveguide; at PsiQuantum's measured 1.8 ± 0.2 dB/m single-mode SiN loss that is ~27 dB against a per-photon budget near 0.5 dB. The same delay in fibre costs ~4 mdB plus two fibre-to-chip transitions at 52 ± 12 mdB D[169]. Feed-forward delay must live off-chip; its loss price is packaging, not waveguide S. Past ~1 GHz the wall becomes SNSPD dead time.

June 2026 reset the arithmetic: 80 ns against a 1 µs cycle is ~12×, and rack electronics at 150–196 ns cut it to ~2×. That array's zero static power costs 1.48 dB per cell, ~15× PsiQuantum's 100 mdB in-line switch D[169], [516] — routing plane, not fusion plane.

The three 2026 latency figures sit at different reference planes, and no source reconciles them. The 27 dB on-chip against 4 mdB in-fibre delay comparison is derived from published loss figures, not measured. Not published: a cost per modulator or per feed-forward channel.

TFLN comes from two merchant vendors, HyperLight and Lightium P[518]; volume BTO only from PsiQuantum's 300 mm GlobalFoundries flow D[169] and Lumiphase's pilot D[516]; Xanadu's 0.085 dB/facet coupling used Corning and DISCO C[172]. No cost per channel is public. I/O burden is this node: a driver and DAC per modulator, a coax and discriminator per detector. QuiX's unit is 32×32 C[825], so 10³ modes is ~30 racks; at 10⁴ the wall is inter-rack clock skew, at 10⁶ nothing scales. The machine falls under BIS ECCN 4A906 fact.

Shared, not an architecture choice: it drives the fusion architecture (PsiQuantum, Quandela, QuiX) and the continuous-variable/GKP architecture (Xanadu) identically, also serves the boson sampler, and sets the derived clock wherever fusions or homodyne measurements iterate — 1.0 MHz at system scale, 5–7 MHz at unit scale. Verification: the figures sit at three reference planes. QuiX's ~150 ns is detector-to-drive C[825]; 196 ns a full CV loop P[822]; Aurora's 1 MHz a cycle time, not a latency D[173].

Money.
2024-09 · HyperLight · Series B · USD 37 M · Summit Partners · closed P[518]
2025-07-10 · QuiX · Series A · EUR 15 M · Invest-NL, EIC · closed Cfact
2026-05-21 · GlobalFoundries · CHIPS LOI · USD 375 M · US Commerce fact
2026-07-22 · PsiQuantum · QBI Stage C, BTO-switch V&V · USD 125 M · DARPA P[181]

Market & supply chain. Two TFLN vendors, one volume BTO line, and no merchant vendor of low-latency feed-forward at all — each firm builds its own. The scarce input is the deterministic sub-200 ns detector-to-driver path, not the modulator. Pays for G3/G4, G6.

IP & standards. No feed-forward patent family surfaced from a dated database as of 2026-09-04; the BTO gate array is the dated advance D[516].

Roadmaps & track record. Xanadu 1 MHz (delivered 2025-01, unimproved) D[173]; QuiX named fast feed-forward a 2026 blocker in 2025-07 and installed the unit 2026-06-02 C[825]; PsiQuantum published no 2026 hardware result P[181]. QuiX alone shipped what it named.

Strategic reading. If sub-200 ns loops generalise, the bottleneck migrates to detector dead time and the fibre delay lines holding photons during the decision — favouring owners of packaging and detector supply over FPGA vendors. A merchant feed-forward box would commoditise a layer three firms treat as differentiation.

Confirm by 2027: a loop under 200 ns above 32 channels, or a system cycle faster than 1 MHz; demote if Aurora's 1 MHz still stands in 2028. Best case 2029: ~10 MHz rack-scale. Worst case: unit latency never couples to scale. Open: does 150 ns hold under 32-channel load; does non-volatile BTO reach usable in-line loss.