Belenos
Belenos
Register profile — the machine's variant of its architecture
qubit type: single photon from a semiconductor quantum dot in a micropillar cavity
gate mechanism: post-selected/heralded linear-optical two-qubit gates in a reconfigurable interferometer mesh
connectivity: reconfigurable interferometer mesh
control: electro-optic control
control placement: room-temp electro-optic
readout: SNSPD
gate evidence: no published figure
flags: no published error rates, source not confirmed
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | Single photon (discrete variable) · primary ▣ Fig. 1 (QD single-photon source at 5 K, active demux, 12-mode chip); SI §S-I + Fig. S1 ✅ single photons from a semiconductor quantum-dot micropillar source, demultiplexed into many modes; qubit count bounded by source brightness ÷ demux loss |
| 2 Encoding | Time-bin / path photonic encoding · primary ▤ Methods: Architecture (path-degree-of-freedom encoding) ✅ path/time-bin-encoded single-photon qubits from one demultiplexed QD source; 12 qubits (Belenos, 22 May 2025) Dual-rail (erasure) encoding · alternate ▤ Methods: Architecture (path-degree-of-freedom encoding) ✅ dual-rail path encoding (Quandela also uses polarisation encodings) |
| 3 Gate mechanism | Linear-optical fusion (heralded) · primary ▣ §III Benchmarking logic gates; SI §S-V + Fig. S9 (post-selected CNOT circuit) ✅ post-selected/heralded linear-optical 2Q gates in a reconfigurable mesh, not FBQC fusion; Ascella 1Q 99.6%, 2Q 93.8%, 3Q 86%; no Belenos fidelity public Multi-photon resource-state generator (RSG; 6-ring etc.) · alternate ▦ 🔎 resource-state route announced but undemonstrated; shipped machines run post-selected linear-optical gates |
| 4 Connectivity / transport | Photonic switching / routing (electro-optic, feed-forward) · primary ▣ Fig. 1 (architecture); Methods: Architecture (12-mode universal interferometer) ✅ reconfigurable linear-optical interferometer mesh fed by the demultiplexed QD source |
| 5 Control | Electro-optic drive + feed-forward electronics (room temperature) · primary ▣ §II Chip control; SI §S-IV + Fig. S8 (phase-shifter voltage model) ✅ electro-optic control, room temperature; no clock rate or source brightness public |
| 6 Readout | Single-photon detection (SNSPD / TES) · primary ▤ Methods: Architecture (12 SNSPD outputs + time-to-digital converter) ✅ SNSPD single-photon detection |
| 7 Code | — none — nothing in this layer ▦ 🔎 no QEC demonstrated; no code family named for the 50-logical-by-2028 roadmap milestone |
| 8 Decoder | — none — nothing in this layer ▦ 🔎 no decoder published; compilers and decoders dedicated to error correction scheduled for 2027 |
| 9 Interconnect | Fibre links between photonic modules · alternate ◌ 🔎 alternate only: no fibre inter-module link published |
| 10 Manufacturing | III-V MBE heterostructures (InAs–Pb wires, QD sources) · alternate ▤ SI §S-I Single-photon source (InGaAs QD in monolithic micropillar) ✅ GaAs quantum-dot single-photon source (III-V heterostructure) Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) · alternate ▤ Methods: Architecture (12-mode Si3N4 photonic integrated circuit) ✅ SiN/silica interferometer meshes (photonic IC); foundry not stated — (Atlas gap: ∅G-twofab) · primary ▤ Methods: Architecture (Si3N4 PIC); SI §S-I (InGaAs QD micropillar source) ✅ needs two L10 nodes: SiN/silica interferometer meshes (fab_pic) plus GaAs quantum-dot source (fab_mbe); the Atlas allows one |
Standard records
2Q error under full-width parallel operation → 0.062 · typical (1 - 0.938, Ascella)
Jun 2023 · source
evidence: ✅ 10 / 15