Boson sampler on the map bar: Boson sampling
Boson sampler
Derived clocks
- syndrome round
- —
- measured cycle
- n/a — sampling; MHz-class clock, no cycle
- reaction time
- 1.0 µs (published loop) · floor —
- coherence
- T1 — · T2 — · ops per coherence —
- idle exposure per round
- t_round/T2 = — · measured idle error —
- notes
- measurement-driven photonic architecture: no syndrome round; native clock in the measured column; no code on this architecture
Technologies by layer — primary, then alternates
| 1 Qubit carrier | Squeezed light mode (CV) · Single photon (discrete variable) |
| 2 Encoding | — no encoding layer — photon-number sampling |
| 3 Gate mechanism | Programmable linear-optical interferometer (no entangling primitive) |
| 4 Connectivity / transport | Photonic switching / routing (electro-optic, feed-forward) |
| 5 Control | Electro-optic drive + feed-forward electronics (room temperature) |
| 6 Readout | Single-photon detection (SNSPD / TES) |
| 7 Code | — no code — sampling |
| 8 Decoder | — no decoder — sampling |
| 9 Interconnect | — no interconnect — one interferometer |
| 10 Manufacturing | Bulk-optics and fibre assembly (photonic samplers) · Photonic IC foundry (SiN, BTO, TFLN, SNSPD on 300 mm) |
Relations within the architecture
Machines of this architecture · 7
- PT-1 ORCA Computing paper product page
- PT-2 ORCA Computing product page press
- Jiuzhang (1.0) USTC (Pan Jianwei group) press
- Jiuzhang 2.0 USTC (Pan Jianwei group) paper press
- Jiuzhang 3.0 USTC (Pan Jianwei group) paper press
- Jiuzhang 4.0 USTC (Pan Jianwei group) paper press
- Borealis Xanadu paper link
The architecture in the report (§8.3)
8.3.12 Boson sampling — Boson sampler (ph_sampler)
The idea. Squeezed light or single photons enter a Programmable linear-optical interferometer (g_lointer) and are counted at its outputs; the output probabilities are hafnians of matrices built from the network (permanents for single photons), #P-hard to compute [G][268]. No entangling gate, no feed-forward, no qubit: the only claim is that no classical computer reproduces the samples (goal G1). Where the fusion architecture builds qubits from small resource states and the continuous-variable architecture encodes them in GKP grids, this architecture skips the qubit. The bet: at high photon number the statistics outrun classical samplers before loss hands the output back to them.
What it needs. The interferometer requires light in the mesh and room-temperature electro-optic phase shifters; Bulk-optics and fibre assembly (fab_bulk) requires fibre-coupled modulators and delay loops. The carriers replace each other, as do photon counting and homodyne detection, and bulk assembly and the photonic IC foundry. Everything else is transmission: noisy Gaussian boson sampling becomes efficiently simulable once squeezing, transmission and detector efficiency fall below a bound [S][269]. Code, decoder and interconnect are ∅ by design (§7.3): a sample has no logical state to protect, so loss is modelled rather than corrected, and classical challengers exploit it [175].
Where it stands. Seven machines, seven devices, none gate-capable (Table 8.3). Jiuzhang 4.0 (USTC, May 2026): 1,024 squeezed states in 8,176 modes, up to 3,050 detected photons, 51% system efficiency, one sample per 25.6 µs [D][175]. Borealis (Xanadu, 2022): 216 squeezed modes through three fibre loops, TES number-resolving detectors, up to 219 photons, one sample per 36 µs [D][270]; the register flags its claim eroded. PT-2 (ORCA, deployed 2024–26) samples photon-subtracted squeezed states in a two-loop time-bin interferometer with a number-resolving detector [P][271]; ORCA publishes no mode count, clock or loss; its earlier PT-1 (two systems at PSNC Poznań, 2023) [C][877] and the retired Jiuzhang 1.0, 2.0 and 3.0 [D][460], [462], [878] are rows of their own. For the register the ∅ layers mean three things: no sampler enters the gate, code or decoder counts; their 21 none cells in layers 7–9 are the architecture, not a delay, and inflate Table 8.2's maturity profile; seven of photonics' eleven devices (Table 8.1) are samplers, so the family's device count overstates its processors.
Exceptions and borrowings. Jiuzhang 4.0 and Borealis hold CV Gaussian gates, the continuous-variable architecture's technology, as an off-slot layer-3 alternate: a Gaussian interferometer without homodyne feed-forward. That is lineage, not mislabelling; Borealis's successor is Aurora. Both leave layer 2 none. The encoding technology, Time-bin / path photonic encoding, rests on PT-2 alone and fits badly: PT-2 fills every time bin, nominally one photon each [P][271], so its bins are modes, not the two-bin qubit the technology defines; and the technology requires a single-photon carrier, while PT-2's is squeezed light. No machine uses the single-photon or homodyne alternates either: in layers 1, 2 and 6 the architecture is drawn wider than its register.
The next test. By 31 December 2027: no published classical sampler matches Jiuzhang 4.0 on its own benchmarks, and ORCA publishes PT-3's modes, loops and loss with a classical comparison. Demote if a classical algorithm matches Jiuzhang 4.0, as one matched each earlier advantage claim, or if PT-3, due in 2026 and undelivered (§2.5), ships without those figures.
What the builders say. USTC presents Jiuzhang 4.0 as more than a sampler: Gaussian boson sampling can also generate bosonic error-correcting codes [D][175], and control of thousands of photons, it says, reaches far beyond classical tractability and opens a path to fault-tolerant photonic hardware [D][175]. ORCA's case is time multiplexing: fibre delays let each photon source be reused many times [C][858]. In May 2025 its chief executive expected quantum advantage within 24 months, from PT-3, then due in early 2026 [R][859]; in June 2026 ORCA installed a PT-2 at a Japanese enterprise and scheduled its upgrade to PT-3 for later in the year [R][860].
Machines of this architecture (register: 7, of them 7 devices, 0 gate-capable). USTC (Pan Jianwei group) — Jiuzhang (1.0) (retired), Jiuzhang 2.0 (retired), Jiuzhang 3.0 (retired), Jiuzhang 4.0 (demonstrated); ORCA Computing — PT-1 (deployed), PT-2 (deployed); Xanadu — Borealis (deployed).
Cells outside the architecture's slots (2). Jiuzhang 4.0: L3 CV Gaussian gates + GKP-assisted non-Gaussian operations (g_cv, alternate borrowed from another architecture); Borealis: L3 CV Gaussian gates + GKP-assisted non-Gaussian operations (g_cv, alternate borrowed from another architecture).