Kunlun

Raveh Neeman

doi:10.5281/zenodo.22674814

Tsinghua University IIIS (D.-L. Deng) with Zhejiang University (H. Wang, C. Song groups)

Kunlun

Tsinghua University IIIS (D.-L. Deng) with Zhejiang University (H. Wang, C. Song groups) · superconducting circuits · DEMONSTRATED (May 2025 (arXiv; Nature Physics, Jan 2026)) · 32 physical qubits · access: lab-only

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: transmon

gate mechanism: tunable coupler

connectivity: long-range couplers; weight-6 non-local stabilisers

control: room-temperature RF

control placement: room-temp

readout: dispersive

gate evidence: no published figure

decoder mode: offline — syndromes decoded after the run

codes: qcga, stab_18_6_3

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▣ Fig. 1a (Kunlun 32-qubit layout: 18 data + 14 check qubits); SI: Device Information; Fig. S4 ✅ 32 long-range-coupled transmons (May 2025)
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to \|2⟩ is the price.
3 Gate mechanism	Tunable-coupler CZ / iSWAP · primary ▣ Fig. S5 (parallel CZ gates); SI: Multi-length couplers; SI: Single- and two-qubit gates ✅ tunable coupler
4 Connectivity / transport	Long-range on-chip couplers (c-couplers, mm-scale) · primary ▣ Fig. 1a (84 couplers in four length sets, long-range in purple); Fig. 2a; SI: Multi-length couplers ✅ long-range couplers on a 32-transmon lattice; weight-6 non-local stabilisers realised (May 2025)
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▤ 🔎 room-temperature RF
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ▣ Fig. S6 (readout resonator frequencies, dispersive shift χ); SI: Measurement setup ✅ dispersive
7 Code	Non-local qLDPC codes (bivariate bicycle, 'gross') · primary ▣ Fig. 1d, Fig. 3 ([[18,4,4]] BB code, logical error per cycle); Extended Data Figs. 1–3 ([[18,6,3]]) ✅ qcga/generalized_bicycle d=4 (4 logical) at 8.91(17)% logical error per cycle; qLDPC d=3 (6 logical) at 7.77(12)%; single distance each (May 2025)
8 Decoder	— none — nothing in this layer ▤ Methods: Decoding; §Decoding and logical error rates ✅ no real-time decoder; decoding offline
9 Interconnect	— none — nothing in this layer ◌ 🔎 monolithic single module, no interconnect
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▣ Fig. 1a right (magnified coupler crossing microstructure); SI: Multi-length couplers ✅ Superconducting-qubit lithography (Nb/Al JJ, 300 mm) — IBM Albany 300 mm / Anderon foundry; Google Santa Barbara; Rigetti ABAA trimming (97.4% frequency-targeting success); OQC 500-qubit wafer-scale…

Standard records

idle / memory error per round → 0.0891 · the only on-hardware bivariate-bicycle measurement (logical error per cycle at d=4)

May 2025 · source

evidence: ✅ 7 / 10

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 1 — Fig. 1: Implementation of the bivariate bicycle code. a, Schematic of the Kunlun processor. (Upper left) Tanner graph of the bivariate bicycle (BB)… — A four-panel figure of renders, not photographs: the Tanner graph of the [[18,4,4]] bivariate bicycle code on a torus, a layout of the 32-qubit superconducting processor Kunlun (18 data and 14 check qubits), a 10 µm inset of two couplers crossing, plus error, timing and circuit panels. From "Demonstration of low-overhead quantum error correction codes" by Ke Wang, Zhide Lu and co-authors. It shows how a qLDPC code that needs non-local connections is laid out on a flat chip with long-range couplers that cross over one another. “Fig. 1 — Fig. 1: Implementation of the bivariate bicycle code. a, Schematic of the Kunlun processor. (Upper left) Tanner graph of the bivariate bicycle (BB) code…” by Ke Wang et al., arxiv.org/abs/2505.09684, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)