Rigetti Ankaa-2
Rigetti Ankaa-2
Register profile — the machine's variant of its architecture
qubit type: tunable transmon + tunable couplers
gate mechanism: native iSWAP
connectivity: square lattice, degree <=4
control: room-temperature RF; Collision Clustering decoder on FPGA in the loop
control placement: room-temp
readout: dispersive
gate evidence: a benchmark paper with its protocol
decoder mode: feed-forward — the decoder's result acts inside the run (closed loop)
codes: rotated_surface
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to |2⟩ is the price. |
| 3 Gate mechanism | Tunable-coupler CZ / iSWAP · primary ▣ Fig. 2e–j (CZ gate layers on hardware edges); Methods: Ankaa-2 device specifications ✅ tunable-coupler 2Q gate, native iSWAP |
| 4 Connectivity / transport | Static nearest-neighbour lattice · primary ▣ Fig. 1b (Ankaa-2 sublattice to readout units); Fig. 2 (hardware connectivity edges) ✅ 84 q square lattice, degree ≤4 |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▣ Fig. 1a (QPU + control system with FPGA decoder); Methods: Description of control system ✅ room-temperature RF control; Riverlane FPGA decoder in the loop, 9.6 µs total reaction for 9 rounds (6.5 µs decode + 3.1 µs communication) |
| 6 Readout | Dispersive microwave readout (+TWPA, Purcell) · primary ▣ Fig. 1b (multiplexed readout feedlines to RX/TX cards); Fig. 1a (latency A–B) ✅ dispersive |
| 7 Code | Rotated surface code (+ yoked variants) · primary ▣ Fig. 2a (stability patch); Fig. 3a (logical error vs rounds) ✅ 8-qubit stability experiment on a rotated planar surface-code patch, real-time FPGA Collision Clustering decoding, no post-selection; logical error 28.1(1)% at 5 rounds → 20.5(1)% at 25 rounds |
| 8 Decoder | FPGA real-time decoders (LCD, Deltaflow) · primary ▣ Fig. 3c–d (FPGA decode time at 156.25 MHz); Fig. 4 (response time); Methods: FPGA decoder integration ✅ Collision Clustering (union-find class) on FPGA, in loop; 0.44–0.79 µs per round at 156.25 MHz; 9.6 µs reaction for 9 rounds |
| 9 Interconnect | |
| 10 Manufacturing |
Standard records
decode latency per round → 440 ns · best in-loop for a non-Google superconducting machine (per round; range 0.44-0.79 us)
Jun 2026 · source
feed-forward latency → 9.6 µs · best measured superconducting reaction time (9 rounds)
6.5 us decode + 3.1 us communication · Jun 2026 · source
evidence: ✅ 7 / 10
Pictures
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