Crossbar shared-line control (spins) cx_crossbar

A crossbar shares gate lines across rows and columns of a dot array: an n×m grid needs O(n+m) lines, not O(nm), at the price that every pulse reaches every dot on the line. Selectivity comes from cross-capacitance compensation and the operating-point spread between tiles: addressing becomes calibration. Proposed for spin qubits by Li et al. (QuTech, Sci. Adv. 2018); first demonstrated by Borsoi et al. (Veldhorst group, QuTech/TU Delft): 16 germanium dots on 23 lines, published January 2024 D[520]. Attributes: connectivity — shared row/column addressing, carrier immobile; control and error — low-frequency drive from room temperature, coherent shared-line crosstalk over ordinary charge noise, CMOS fabrication.

Line count follows a Rent exponent near 0.5: T = 6√g − 1 terminals for g dots D[520], and n+m+7 = 53 lines for the 23×23 QARPET array, capacity 1,058 sites at 2×10⁶ tiles/mm² D[521]. The binding constraint is uniformity, not wiring: one shared voltage must land inside every tile's operating window at once, so threshold spread sets how many tiles a line serves. QARPET's 38-of-40 addressable tiles show T2* 4.43–5.75 µs and Hahn-echo T2 10.11–12.69 µs, comparable to individually wired germanium devices: sharing lines costs no coherence D[521]. What it adds is coherent error correlated along a whole row or column, the structure decoders assume away. On-chip demultiplexing would move the floor.

Dominant term: addressing coverage. Neither device published a two-qubit gate on a shared line.

Not published: a shared-line crosstalk figure for any crossbar array; the conflict with per-pair exchange calibration follows from the addressing scheme, not from a measurement.

Both devices are Ge/SiGe heterostructures made in a university cleanroom, not on a 300 mm line, and no foundry has announced a crossbar process step as of 4 Sep 2026 — GlobalFoundries' Quantum Technology Solutions unit, with cryogenic control ICs and packaging, is the closest named capability C[353]. Control burden is the whole point, and its cost reappears as sequencing: one row and one column select at a time, so at 10³ tiles parallel operation needs on-chip decoding, and at 10⁴–10⁶ the wall is addressing bandwidth, not connector count. No demultiplexer has been demonstrated inside an array.

Requires a gate-defined quantum-dot spin carrier; replaces one-line-per-electrode wiring; conflicts with per-pair exchange calibration, since a shared barrier cannot deliver an independently tuned pulse to every pair at once. Belongs to the silicon and germanium quantum-dot spin architecture. Its clock contribution is a sequencing multiplier on derived clock = sum of the syndrome round: gate layers + transport + readout + reset (8.5 µs here, readout-set), unquantified in any publication. Verification: 1,058 is a site capacity, not a qubit count, and no crossbar has published a two-qubit fidelity, a crosstalk figure or a replication. The "only some pairs work" result often cited here — one of four pairs gated on imec's eight-qubit 300 mm device D[197] — is individually wired, not a crossbar.

Who.
| Organisation | Role | Country | What they do | Evidence |
|---|---|---|---|---|
| QuTech/TU Delft | research | Netherlands | Built both crossbar devices, including QARPET | D[521] |
| Groove Quantum | developer | Netherlands | Commercialises the germanium dot platform | fact |
| GlobalFoundries | supplier | USA | Cryogenic control ICs and packaging | C[353] |
| Quantum Machines | supplier | Israel | Sequencing hardware for shared-line addressing | C[449] |

Money. 2026-04-30 · Groove Quantum · venture round · €16 M · investors undisclosed · €26 M cumulative · closed fact. 2026-05-21 · GlobalFoundries · CHIPS letter of intent · $375 M · US Commerce · non-binding fact.

Market & supply chain. No crossbar-specific equipment vendor exists; the scheme sets how many fridge lines an array needs, making cryogenic control ICs the contested layer C[353]. Pays into G3 and G4 only — below ~10³ dots individual wiring is cheaper and better characterised.

IP & standards. No dated crossbar patent family found in a named database as of 4 Sep 2026; the shared-line principle is commodity-memory word-line addressing, long out of patent.

Roadmaps & track record. QuTech (2026-02-12 · QARPET as a shared benchmarking chip · delivered, no scaling roadmap) D[521]. Diraq's 2029 roadmap names no wiring scheme Rfact. The demonstrations are modest and honestly stated; no vendor has committed to a crossbar.

Strategic reading. If crossbars scale, leverage shifts from rack-electronics vendors to whichever foundry can put demultiplexers at millikelvin; if uniformity blocks them, per-qubit wiring with cold multiplexing — the HRL/IBM route — wins and the rack vendors keep their position.

Confirm or demote in 12–24 months: two tiles gated independently through one shared line; a published crosstalk figure; a foundry crossbar step by 2027. Best case 2029: on-chip demultiplexing addresses >10⁴ dots with hundreds of lines. Worst case: crossbars stay a wireability demonstration while cold per-qubit multiplexing wins. Open: (1) what fraction of tiles stays addressable as arrays grow; (2) whether row-correlated error breaks decoder assumptions; (3) whether demultiplexers fit the millikelvin power budget.