Rigetti Cepheus-1-108Q

Raveh Neeman

doi:10.5281/zenodo.22674814

Rigetti Computing · superconducting circuits · DEPLOYED (7 Apr 2026) · 108 physical qubits · access: cloud service (QCS + Braket), 20 h/day window

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: tunable transmon

gate mechanism: tunable couplers within chiplets + inter-module couplers (IMCs); adiabatic CZ ~60 ns

connectivity: square lattice per chiplet tiled to 108 sites, degree <=4

control: room-temperature RF; ABAA junction frequency trimming (the 97.4% targeting-yield figure is not in the cited page)

control placement: room-temp

readout: dispersive (fidelity not in the release)

gate evidence: a published figure (source class not yet tagged)

flags: roadmap date missed

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▣ Fig. 1a-c (circuit diagrams: qubits Q1/Q2 on separate chips joined by floating multi-chip coupler); Fig. 3 (photomicrograph of assembled test device) ✅ tunable transmon; 108 q = twelve 9-qubit chiplets in a 3×4 array; GA 7 Apr 2026
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to \|2⟩ is the price.
3 Gate mechanism	Tunable-coupler CZ / iSWAP · primary ▣ §II.A Design of a floating tunable coupler; Fig. 4 (net qubit-qubit coupling, g=0 point); Fig. 6 (CZ RB on Four-Bump device); §III.C ✅ tunable couplers + inter-module couplers; adiabatic CZ ~60 ns (replaced iSWAP); median 2Q 99.1%, 1Q 99.9% (Apr 2026); prototype CZ 99.9% at 28 ns
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▨ 🔎 square lattice per 9-q chiplet, degree ≤4, tiled to a 108-site lattice
5 Control	Room-temperature electronics + per-qubit coax/flex · primary ▤ §II.B Multi-chip tunable coupler assembly (flux-bias and readout lines integrated into the carrier chip) ✅ room-temperature RF control
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ▤ §II.B (one readout resonator per qubit; readout lines routed through the carrier chip) 🔎 dispersive; readout fidelity and T1/T2 not in the release
7 Code	— none — nothing in this layer ▨ 🔎 no QEC code run on Cepheus (NISQ)
8 Decoder	— none — nothing in this layer ▨ 🔎 no decoder (no QEC)
9 Interconnect	Multi-chip modules / l-couplers (same cryostat) · primary ▣ Fig. 1a-c (Bump-Paddle, Bump-Bump, Four-Bump multi-chip coupler designs on a common carrier chip); Fig. 3 (assembled device); Fig. 5 (coherence with indium bumps); §II.B ✅ twelve 9-q chiplets (3×4 MCM) joined by inter-module couplers; median 2Q 99.8% (9 q) → 99.6% (36 q) → 99.1% (108 q), Apr 2026
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ▤ §II.C Fabrication (qubit chips by standard lithography on high-resistivity Si; indium bump bonding to carrier) ✅ in-house Fab-1 (Fremont); chiplet MCM — (Atlas gap: ∅G-calib) · alternate ▨ ✅ ABAA (alternating-bias assisted annealing) post-fab JJ frequency targeting, 97.4% success (Aug 2024)

Standard records

2Q error under full-width parallel operation → 9.00e-3 · typical (median 2Q at 108 q, 99.1%)

Apr 2026 · source

parameter spread → 0.99 · measured fidelity-versus-tiling degradation (99.8% at 9 q, 99.6% at 36 q, 99.1% at 108 q)

the most useful public datum about chiplet scaling · Apr 2026 · source

device yield → 0.974 · best (frequency-targeting success via ABAA)

Aug 2024 · source

evidence: ✅ 6 / 11