RIKEN 64-qubit superconducting processor

Raveh Neeman

doi:10.5281/zenodo.22674814

RIKEN with AIST, NICT, Osaka University, Fujitsu, NTT

RIKEN 64-qubit superconducting processor

RIKEN with AIST, NICT, Osaka University, Fujitsu, NTT · superconducting circuits · DEPLOYED (27 Mar 2023) · 64 physical qubits · access: cloud service (non-commercial)

architecture: Transmon lattice with tunable couplers · Open on the map

Register profile — the machine's variant of its architecture

qubit type: transmon

gate mechanism: coupler type not published (fixed vs tunable unresolved)

connectivity: 2-D square arrangement of unit cells

control: microwave drive at 8-9 GHz; perpendicular ("3-D vertical") wiring package

control placement: room-temp

readout: dispersive

gate evidence: no published figure

flags: no published error rates, source not confirmed

Technologies by layer — the machine's cell per layer

1 Qubit carrier	Transmon · primary ▥ Fig. 1 (64-qubit two-dimensional integrated circuit chip; 16 basic units of 4 qubits) ✅ transmon; 64 q as 16 four-qubit unit cells on a single ~2 cm silicon chip
2 Encoding	Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to \|2⟩ is the price.
3 Gate mechanism	Tunable-coupler CZ / iSWAP · alternate ▨ 🔎 coupler type not published (fixed vs tunable unresolved); g_tc is nearest technology — undisclosed — exists, nothing published ▨ 🔎 gate mechanism not published; no official source states fixed capacitive vs tunable coupling
4 Connectivity / transport	Static nearest-neighbour lattice · primary ▥ Fig. 1 (16 basic units of 4 qubits arrayed in a square); Fig. 6 (periodic planar tiling of 4-qubit units) ✅ 16 four-qubit unit cells in a 2-D square arrangement on one ~2 cm chip (64 q)
5 Control	Vertical (out-of-plane) signal delivery — VIO, coaxmon, 3D wiring · primary ▥ Fig. 2 (perpendicular wiring package: control/readout lines via contact probes); Fig. 5 (wiring in DR) ✅ perpendicular ("3-D vertical") wiring package: signals brought in normal to the chip plane, not routed laterally; reused by Fujitsu at 256 q Room-temperature electronics + per-qubit coax/flex · alternate ▥ Fig. 3 (qubit controller: microwave oscillator + receiver; 96 input / 16 output wires) ✅ room-temperature microwave drive at 8–9 GHz into a dilution refrigerator
6 Readout	Dispersive microwave readout (+TWPA, Purcell) · primary ▥ Fig. 3 (16 output wires for readout, microwave receiver); Fig. 2 (readout wiring) ✅ dispersive
7 Code	— none — nothing in this layer ▨ 🔎 no QEC code run (NISQ); hybrid error-mitigation evaluation with Fujitsu 40-qubit simulator
8 Decoder	— none — nothing in this layer ▨ 🔎 no decoder (no QEC)
9 Interconnect	— none — nothing in this layer ▥ Fig. 1 (single 64-qubit chip); Fig. 5 (one chip in central magnetic shield) ✅ monolithic single ~2 cm chip, no interconnect
10 Manufacturing	Superconducting-qubit lithography (Al/AlOx/Al junctions, Nb wiring, 300 mm) · primary ◌ 🔎 Superconducting-qubit lithography (Nb/Al JJ, 300 mm) — IBM Albany 300 mm / Anderon foundry; Google Santa Barbara; Rigetti ABAA trimming (97.4% frequency-targeting success); OQC 500-qubit wafer-scale…

evidence: ✅ 6 / 12

Pictures

Every picture carries the story of what it shows and its credit line.

Fig. 9 — Figure 9: Images of the 64-qubit device. (a) Photograph of the 64-qubit chip. The unit cell containing the measured qubit is highlighted. (b) False-… — Two optical images: (a) a photograph of a whole 64-qubit superconducting chip (5 mm scale bar) tiled with sixteen four-qubit unit cells over a regular grid of dark circular features; (b) a false-coloured close-up (1 mm scale bar) of one unit cell with readout resonators, filter resonators, qubits, qubit–qubit couplers and, at its centre, a through-silicon via connecting to the readout feedline. It is Figure 9 of arXiv 2608.25484 by Spring, Hesse, Wang, Tamate and Nakamura. It shows out-of-plane wiring in practice: signals reach the middle of a large qubit array through the substrate instead of from the chip edge. “Fig. 9 — Figure 9: Images of the 64-qubit device. (a) Photograph of the 64-qubit chip. The unit cell containing the measured qubit is highlighted. (b) False-colored…” by Peter A. Spring, Adrian L. Hesse, Shiyu Wang, Shuhei Tamate, Yasunobu Nakamura, arxiv.org/abs/2608.25484, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)