QpiAI Indus
QpiAI Indus
Register profile — the machine's variant of its architecture
qubit type: transmon
gate mechanism: tunable coupler (assumed)
connectivity: not published
control: room-temperature RF; full in-house stack (QPU + control + mK cryogenics + Quantum-HPC)
control placement: room-temp
readout: dispersive
gate evidence: no published figure
flags: no published error rates, source not confirmed
Technologies by layer — the machine's cell per layer
| 1 Qubit carrier | |
| 2 Encoding | Bare physical qubit (no encoding) · primary ◌ 🔎 Bare two-level subspace — Computational subspace of an anharmonic oscillator; leakage to |2⟩ is the price. |
| 3 Gate mechanism | |
| 4 Connectivity / transport | |
| 5 Control | Room-temperature electronics + per-qubit coax/flex · primary ▨ ✅ room-temperature RF; full in-house stack: QPU + control + mK cryogenics + Quantum-HPC (deployed 14 Apr 2025) |
| 6 Readout | |
| 7 Code | |
| 8 Decoder | |
| 9 Interconnect | |
| 10 Manufacturing |
evidence: ✅ 1 / 10