Algorithmic FT / transversal architectures code_aft

Algorithmic fault tolerance, introduced by Zhou, Bluvstein, Kubica, Lukin and co-workers as a preprint in June 2024 and published in Nature in 2025 D[152], runs logical gates transversally between code blocks and decodes the algorithm's whole syndrome history jointly, so a logical gate costs a constant number of extraction rounds rather than the O(d) lattice surgery needs.

Mobility: it presumes a machine that can bring any two blocks into register — tweezer transport or ion shuttling — not a fixed lattice. Error structure: no new channel — the code's own Pauli and erasure noise, atom loss dominant, with physical-cycle overhead traded for classical decoding overhead.

The d-round rule exists because one round cannot distinguish a measurement error from a data error; repeating the syndrome circuit d times makes the detector graph's spacetime distance equal the code distance. That redundancy is only needed when each block is decoded alone: a transversal CNOT maps a fault in one block to its partner in the other, so the joint graph across blocks and time still has distance d after O(1) rounds — if the decoder uses it. The proof bounds deviation from the ideal logical measurement distribution as exponentially small D[152].

The cost moves to the classical side, structurally. The joint graph does not factorise, so the sliding window that keeps per-block decoding local in time is no longer exact: the decoder spans several logical gates, cannot close its window until the next feed-forward point, and its work grows with the blocks entangled since the last measurement, not with d.

Every reported gain is simulation or an offline decode of stored syndromes: no published run closes the loop — transversal gate, correlated decode, feed-forward — in real time.

An architecture and decoding layer with no process, yield or unit cost. Its supply-chain exposure is second-hand but specific: crossed acousto-optic deflectors, where AA Opto-Electronic and Gooch & Housego are the only vendors named in the 448-atom work D[4], and the classical hardware running the decode. NVIDIA's NVQLink sets the yardstick at 3.84 µs round trip and 67 µs median decode with BP+OSD (belief propagation plus ordered-statistics decoding) — on the far easier per-block problem C[324].

No new laser, control line or detector; the burden is classical and real-time. A correlated decoder must ingest syndromes from every block touched by a transversal gate and return a correction before the next feed-forward point — within milliseconds on atoms, on a graph 10²–10³× larger than the single-block problem GPUs handle now. At 10³ logical qubits the evidence is simulation; at 10⁴–10⁶ no latency model has been published, and both resource estimates assume decoding keeps up S[31]S[30]. That assumption, not atom count, is where this fails if it fails.

It applies on any architecture that can move qubits: the alkali Rydberg tweezer array (QuEra, Pasqal, Infleqtion) and — though the graph record models it on that array alone — Atom Computing's alkaline-earth(-like) arrays and the trapped-ion QCCD architecture, where Quantinuum runs the same [[16,6,4]] code transversally D[667]. It requires transport plus correlated, loss-aware decoding, and conflicts with fixed nearest-neighbour lattices, which cannot pair arbitrary blocks without a routing layer. It adds no term to the derived clock but multiplies it, cutting rounds per logical gate from ~d (at d=7 on atoms, ~9 ms per gate) to O(1). Neighbouring empty slot: a real-time correlated decoder.

Transversal gates and 96 active logical qubits are hardware measurements D[4]; the >10× reduction is a theorem plus simulation D[152], unreproduced outside the author group. The two resource estimates differ by three orders in space — a trade curve, not a contradiction: 19 M atoms buys RSA-2048 in 5.6 days S[31], while 10,000–26,000 atoms buys P-256 in days and RSA-2048 one to two orders slower S[30]; "RSA-2048 with 10,000 atoms" is what neither paper says. The sharpest counter-evidence is Atom Computing and Microsoft's toric code: Λ_Z ≈ 1.9 but Λ_X ≈ 1.2, average 1.30 over four cycles, and with reloading over 90 rounds suppression vanished (0.63% versus 0.64% per cycle) D[148]. Atoms have not shown sustained below-threshold memory, and constant-round fault tolerance is a claim about long algorithms.

Not published: a common assumption set (physical error rate, code distance, decoder model) for the 19 M-atom / 5.6-day and 10,000-atom estimates, and a real-time correlated-decoder latency above roughly 10² logical qubits. The >10× spacetime reduction has no replication outside the overlapping Harvard/QuEra/Caltech author group.

Who.
| Organisation | Role | Country | What they do here | Evidence |
|---|---|---|---|---|
| Harvard | research | US | Originated the scheme; 448-atom transversal demo | D[4], [152] |
| QuEra | developer | US | Co-author and hardware; Libra 2028 needs the gain | Cfact |
| Quantinuum | developer | US/UK | Transversal logical Cliffords on ions, same code | D[667] |
| Atom Computing | developer | US | Zoned transport; published the counter-result | D[148] |
| Google Quantum AI | developer | US | Neutral-atom track since 2026-03, QEC-focused | C[9] |
| Pasqal | developer | FR | Transport architecture, 100 logical by 2029 | Cfact |

Money. 2025-09-09 · QuEra · round · $230 M+ · Google, SoftBank Vision Fund 2, NVentures · closed G[153]fact. 2025-11-06 · Atom Computing and QuEra · QBI Stage B · ≤$15 M each · active G[65]fact. 2026-02-17 · Infleqtion · IPO · >$550 M · NYSE INFQ G[155]. 2026-05-21 · Atom Computing and Infleqtion · CHIPS LOI · $100 M each · US Commerce · non-binding G[300]fact. 2026-06-16 · Atom Computing · Series C · $100 M, Third Point G[154]fact. 2026-08-28 · Pasqal · SPAC · ~$360 M cash · Nasdaq PSQL G[156]fact.

Market & supply chain. Nothing is sold under this name; it multiplies someone else's machine, so rent accrues to the transport optics and the decoder stack. It pays for G3, cutting physical-per-logical from ~10³ toward ~10², and for G4 if it holds; nothing for G1 or G5.

IP & standards. The founding work is peer-reviewed in Nature and open on arXiv, as is the ISCA resource analysis; no patent family specific to algorithmic fault tolerance or correlated decoding was found as of 2026-09-04.

Roadmaps & track record. QuEra: Libra promised 2026-06-15 for 2028 (>256 logical, 10⁻⁶) after a January 2024 promise of 100 logical qubits in 2026 — a two-year slip, so the schedule now leaning on constant-round fault tolerance has been reset once R[162]fact. Pasqal: 10,000 physical slipped 2026 to 2028 Rfact. Every atom roadmap past 2027 prices in this gain; none names it as a dependency.

Strategic reading. If it holds at scale, every transport-capable vendor's fault-tolerance date moves left at once and the millisecond atom cycle stops being disqualifying — the bet behind zoned architectures. Ions gain equally and are further along on transversal Cliffords, so the winner need not be an atom company. The losers are fixed nearest-neighbour superconducting lattices, which cannot claim the discount.

Confirm/demote in 12–24 months: a group closes transversal gate, correlated decode and feed-forward on hardware; an atom system shows sustained below-threshold memory with reloading; QuEra restates Libra without the gain. Best case 2029: constant-round fault tolerance at 10³ logical qubits, compressing every transport-capable roadmap. Worst case: correlated decoding stalls at a few dozen blocks and stays a resource-estimation tool. Open: does decoder latency scale past 10⁴ blocks; does >10× survive loss-heavy noise. Watch: Libra milestones and any real-time correlated-decoder demonstration.