Rigetti Novera — DEPLOYED (on-prem QPU launched Dec 2023, 'available to ship immediately'; installed at Horizon Quantum, Singapore, and Montana State University QCORE), 9 q, Dec 2023 (launched)
Figure on running an error-correction decoder in real time inside the control system of a superconducting quantum computer. A drawn block diagram of the Rigetti control system shows gate and readout sequencers and a Riverlane real-time decoder within field-programmable gate array (FPGA) boundaries, with each delay marked, such as about 500 ns between sending and receiving a readout pulse. Beside it are a photograph of a dilution-refrigerator insert with a magnified view labelled QPU (quantum processing unit) and a map of qubits Q28–Q60 with a highlighted three-by-three block. From Caune et al., Nature Communications 2026, on the Ankaa-2 processor. It shows where the decoder sits and how fast results travel.“Fig. 1 — Fig. 1: Integration of a hardware decoder into a control system.a Sketch of the Ankaa-2 quantum processing unit (QPU) and control system architecture with the…” by Caune et al., www.nature.com/articles/s41467-026-73331-6, CC BY 4.0 (creativecommons.org/licenses/by/4.0/)
